seg_check.hier_info

基于VHDL的序列检测器设计

|seg_check
clk => q~reg0.CLK
clk => current_state~11.IN1
clr => q~2.OUTPUTSELECT
clr => current_state~10.OUTPUTSELECT
clr => current_state~9.OUTPUTSELECT
clr => current_state~8.OUTPUTSELECT
clr => current_state~7.OUTPUTSELECT
clr => current_state~6.OUTPUTSELECT
clr => current_state~5.OUTPUTSELECT
clr => current_state~4.OUTPUTSELECT
din => current_state~3.DATAB
din => current_state~1.DATAB
din => current_state~2.DATAB
din => Selector0.IN1
din => q~0.OUTPUTSELECT
din => Selector1.IN1
din => Selector2.IN0
din => Selector3.IN0
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE