seg_check.tan.rpt

基于VHDL的序列检测器设计

; N/A   ; None         ; 2.141 ns   ; clr  ; current_state.s5 ; clk      ;
; N/A   ; None         ; 2.132 ns   ; clr  ; current_state.s6 ; clk      ;
; N/A   ; None         ; 2.032 ns   ; din  ; current_state.s6 ; clk      ;
; N/A   ; None         ; 2.031 ns   ; din  ; current_state.s5 ; clk      ;
; N/A   ; None         ; 2.029 ns   ; din  ; current_state.s2 ; clk      ;
; N/A   ; None         ; 2.025 ns   ; din  ; current_state.s0 ; clk      ;
; N/A   ; None         ; 2.024 ns   ; din  ; q~reg0           ; clk      ;
; N/A   ; None         ; 2.024 ns   ; din  ; current_state.s1 ; clk      ;
; N/A   ; None         ; 2.023 ns   ; din  ; current_state.s4 ; clk      ;
; N/A   ; None         ; 2.022 ns   ; din  ; current_state.s3 ; clk      ;
; N/A   ; None         ; 1.586 ns   ; clr  ; current_state.s1 ; clk      ;
+-------+--------------+------------+------+------------------+----------+


+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From   ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A   ; None         ; 9.163 ns   ; q~reg0 ; q  ; clk        ;
+-------+--------------+------------+--------+----+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To               ; To Clock ;
+---------------+-------------+-----------+------+------------------+----------+
; N/A           ; None        ; -1.032 ns ; clr  ; current_state.s1 ; clk      ;
; N/A           ; None        ; -1.468 ns ; din  ; current_state.s3 ; clk      ;
; N/A           ; None        ; -1.469 ns ; din  ; current_state.s4 ; clk      ;
; N/A           ; None        ; -1.470 ns ; din  ; q~reg0           ; clk      ;
; N/A           ; None        ; -1.470 ns ; din  ; current_state.s1 ; clk      ;
; N/A           ; None        ; -1.471 ns ; din  ; current_state.s0 ; clk      ;
; N/A           ; None        ; -1.475 ns ; din  ; current_state.s2 ; clk      ;
; N/A           ; None        ; -1.477 ns ; din  ; current_state.s5 ; clk      ;
; N/A           ; None        ; -1.478 ns ; din  ; current_state.s6 ; clk      ;
; N/A           ; None        ; -1.578 ns ; clr  ; current_state.s6 ; clk      ;
; N/A           ; None        ; -1.587 ns ; clr  ; current_state.s5 ; clk      ;
; N/A           ; None        ; -1.594 ns ; clr  ; current_state.s2 ; clk      ;
; N/A           ; None        ; -1.603 ns ; clr  ; current_state.s3 ; clk      ;
; N/A           ; None        ; -1.605 ns ; clr  ; current_state.s4 ; clk      ;
; N/A           ; None        ; -1.606 ns ; clr  ; q~reg0           ; clk      ;
; N/A           ; None        ; -1.607 ns ; clr  ; current_state.s0 ; clk      ;
+---------------+-------------+-----------+------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Nov 19 13:58:39 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seg_check -c seg_check
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 304.04 MHz between source register "current_state.s0" and destination register "current_state.s1"
    Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.071 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N5; Fanout = 1; REG Node = 'current_state.s0'
            Info: 2: + IC(0.888 ns) + CELL(1.183 ns) = 2.071 ns; Loc. = LC_X1_Y7_N9; Fanout = 1; REG Node = 'current_state.s1'
            Info: Total cell delay = 1.183 ns ( 57.12 % )
            Info: Total interconnect delay = 0.888 ns ( 42.88 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.819 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X1_Y7_N9; Fanout = 1; REG Node = 'current_state.s1'
                Info: Total cell delay = 2.081 ns ( 54.49 % )
                Info: Total interconnect delay = 1.738 ns ( 45.51 % )
            Info: - Longest clock path from clock "clk" to source register is 3.819 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X1_Y7_N5; Fanout = 1; REG Node = 'current_state.s0'
                Info: Total cell delay = 2.081 ns ( 54.49 % )
                Info: Total interconnect delay = 1.738 ns ( 45.51 % )
        Info: + Micro clock to output delay of source is 0.376 ns
        Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "current_state.s0" (data pin = "clr", clock pin = "clk") is 2.161 ns
    Info: + Longest pin to register delay is 5.647 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_12; Fanout = 8; PIN Node = 'clr'
        Info: 2: + IC(3.332 ns) + CELL(1.183 ns) = 5.647 ns; Loc. = LC_X1_Y7_N5; Fanout = 1; REG Node = 'current_state.s0'
        Info: Total cell delay = 2.315 ns ( 41.00 % )
        Info: Total interconnect delay = 3.332 ns ( 59.00 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X1_Y7_N5; Fanout = 1; REG Node = 'current_state.s0'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: tco from clock "clk" to destination pin "q" through register "q~reg0" is 9.163 ns
    Info: + Longest clock path from clock "clk" to source register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X1_Y7_N6; Fanout = 2; REG Node = 'q~reg0'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.968 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N6; Fanout = 2; REG Node = 'q~reg0'
        Info: 2: + IC(2.646 ns) + CELL(2.322 ns) = 4.968 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'q'
        Info: Total cell delay = 2.322 ns ( 46.74 % )
        Info: Total interconnect delay = 2.646 ns ( 53.26 % )
Info: th for register "current_state.s1" (data pin = "clr", clock pin = "clk") is -1.032 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X1_Y7_N9; Fanout = 1; REG Node = 'current_state.s1'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 5.072 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_12; Fanout = 8; PIN Node = 'clr'
        Info: 2: + IC(3.349 ns) + CELL(0.591 ns) = 5.072 ns; Loc. = LC_X1_Y7_N9; Fanout = 1; REG Node = 'current_state.s1'
        Info: Total cell delay = 1.723 ns ( 33.97 % )
        Info: Total interconnect delay = 3.349 ns ( 66.03 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 122 megabytes
    Info: Processing ended: Wed Nov 19 13:58:41 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01