seg_check.flow.rpt

基于VHDL的序列检测器设计

Flow report for seg_check
Wed Nov 19 13:58:40 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------+
; Flow Summary                                                        ;
+--------------------------+------------------------------------------+
; Flow Status              ; Successful - Wed Nov 19 13:58:40 2008    ;
; Quartus II Version       ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name            ; seg_check                                ;
; Top-level Entity Name    ; seg_check                                ;
; Family                   ; MAX II                                   ;
; Device                   ; EPM1270GT144C5                           ;
; Timing Models            ; Final                                    ;
; Met timing requirements  ; Yes                                      ;
; Total logic elements     ; 8 / 1,270 ( < 1 % )                      ;
; Total pins               ; 4 / 116 ( 3 % )                          ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 0                                        ;
; DSP block 9-bit elements ; 0                                        ;
; Total PLLs               ; 0                                        ;
; Total DLLs               ; 0                                        ;
; UFM blocks               ; 0 / 1 ( 0 % )                            ;
+--------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 11/19/2008 13:58:28 ;
; Main task         ; Compilation         ;
; Revision Name     ; seg_check           ;
+-------------------+---------------------+


+-------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                            ;
+------------------------------------+-----------------------------+---------------+-------------+------------+
; Assignment Name                    ; Value                       ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+-----------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID              ; 61026833469.122707430802336 ; --            ; --          ; --         ;
; MAX_CORE_JUNCTION_TEMP             ; 85                          ; --            ; --          ; --         ;
; MIN_CORE_JUNCTION_TEMP             ; 0                           ; --            ; --          ; --         ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off                         ; --            ; --          ; eda_palace ;
+------------------------------------+-----------------------------+---------------+-------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis    ; 00:00:03     ; 1.0                     ; 178 MB              ; 00:00:03                           ;
; Fitter                  ; 00:00:02     ; 1.0                     ; 159 MB              ; 00:00:02                           ;
; Assembler               ; 00:00:02     ; 1.0                     ; 135 MB              ; 00:00:01                           ;
; Classic Timing Analyzer ; 00:00:01     ; 1.0                     ; 110 MB              ; 00:00:01                           ;
; Total                   ; 00:00:08     ; --                      ; --                  ; 00:00:07                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off seg_check -c seg_check
quartus_fit --read_settings_files=off --write_settings_files=off seg_check -c seg_check
quartus_asm --read_settings_files=off --write_settings_files=off seg_check -c seg_check
quartus_tan --read_settings_files=off --write_settings_files=off seg_check -c seg_check