seg_check.vhd.bak

基于VHDL的序列检测器设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity seg_check is
	port(clk:in std_logic;
		 clr:in std_logic;
		 din:in std_logic;
		 q:out std_logic);
end seg_check;

architecture behave of seg_check is

type state_m8 is(s0,s1,s2,s3,s4,s5,s6);
signal current_state:state_m8:=s0;
signal data:std_logic_vector(6 downto 0);
begin
data<="1110010";
process(clk,din)
	begin
	if rising_edge(clk)then
		if clr='1'then
			current_state<=s0;
			q<='0';
		else
			case current_state is
				when s0=>			
					if din=data(6)then------data=1
						current_state<=s1;
					else
						current_state<=s0;
					end if;
					q<='0';
				when s1=>			---1
					if din=data(5)then------data=1
						current_state<=s2;
					else
						current_state<=s0;
					end if;	
					q<='0';				
				when s2=>			---11
					if din=data(4)then------data=1
						current_state<=s3;
					else
						current_state<=s0;
					end if;
					q<='0';
				when s3=>			---111
					if din=data(3)then------data=0
						current_state<=s4;
					else
						current_state<=s3;
					end if;	
					q<='0';									
				when s4=>			---1110
					if din=data(2)then------data=0
						current_state<=s5;
					else
						current_state<=s1;
					end if;	
					q<='0';										
				when s5=>			---11100
					if din=data(1)then------data=1
						current_state<=s6;
					else
						current_state<=s0;
					end if;		
					q<='0';				
				when s6=>			---111001
					if din=data(0)then     ---1110010------data=0
						current_state<=s0;
						q<='1';
					else
						current_state<=s2;
					end if;	
			end case;
		end if;
	end if;
end process;
	
end behave;