seg_check.map.summary

基于VHDL的序列检测器设计

Analysis & Synthesis Status : Successful - Wed Nov 19 13:58:30 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
Revision Name : seg_check
Top-level Entity Name : seg_check
Family : MAX II
Total logic elements : 8
Total pins : 4
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0