decoder.vhd

基于VHDL的电子时钟设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder is
Port (din:in std_logic_vector(3 downto 0 );   --四位二进制码输入
	  dout:out std_logic_vector(6 downto 0));  --输出LED七段码
end decoder;

architecture Behavioral of decoder is
begin
process(din)
begin
case din is
when "0000" => dout<="0000001";--0
when "0001" => dout<="1001111";--1
when "0010" => dout<="0010010";--2
when "0011" => dout<="0000110";--3
when "0100" => dout<="1001100";--4
when "0101" => dout<="0100100";--5
when "0110" => dout<="0100000";--6
when "0111" => dout<="0001111";--7
when "1000" => dout<="0000000";--8
when "1001" => dout<="0000100";--9
when others => dout<="1111111";
end case;
end process;
end Behavioral;