clock.fit.summary

基于VHDL的电子时钟设计

Fitter Status : Successful - Wed Nov 19 22:38:08 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : MAX II
Device : EPM1270T144C5
Timing Models : Final
Total logic elements : 67 / 1,270 ( 5 % )
Total pins : 64 / 116 ( 55 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )