📄 clock.tan.rpt
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Classic Timing Analyzer report for clock
Wed Nov 19 22:38:16 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 32.670 ns ; counter24:u5|count[2] ; hourh[5] ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 185.74 MHz ( period = 5.384 ns ) ; counter24:u5|count[2] ; counter24:u5|count[5] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM1270T144C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Minimum Core Junction Temperature ; 0 ; ; ; ;
; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 185.74 MHz ( period = 5.384 ns ) ; counter24:u5|count[2] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 4.675 ns ;
; N/A ; 189.18 MHz ( period = 5.286 ns ) ; counter24:u5|count[0] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 4.577 ns ;
; N/A ; 195.12 MHz ( period = 5.125 ns ) ; counter24:u5|count[3] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 4.416 ns ;
; N/A ; 198.57 MHz ( period = 5.036 ns ) ; counter24:u5|count[1] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 4.327 ns ;
; N/A ; 203.67 MHz ( period = 4.910 ns ) ; counter24:u5|count[2] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 4.201 ns ;
; N/A ; 203.67 MHz ( period = 4.910 ns ) ; counter24:u5|count[0] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 4.201 ns ;
; N/A ; 203.75 MHz ( period = 4.908 ns ) ; counter24:u5|count[0] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 4.199 ns ;
; N/A ; 205.55 MHz ( period = 4.865 ns ) ; counter24:u5|count[2] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 4.156 ns ;
; N/A ; 213.31 MHz ( period = 4.688 ns ) ; counter24:u5|count[0] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 3.979 ns ;
; N/A ; 215.01 MHz ( period = 4.651 ns ) ; counter24:u5|count[3] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 3.942 ns ;
; N/A ; 217.72 MHz ( period = 4.593 ns ) ; counter24:u5|count[1] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 3.884 ns ;
; N/A ; 219.20 MHz ( period = 4.562 ns ) ; counter24:u5|count[1] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 3.853 ns ;
; N/A ; 222.77 MHz ( period = 4.489 ns ) ; counter24:u5|count[2] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 3.780 ns ;
; N/A ; 222.87 MHz ( period = 4.487 ns ) ; counter24:u5|count[2] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 3.778 ns ;
; N/A ; 225.68 MHz ( period = 4.431 ns ) ; counter24:u5|count[3] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 3.722 ns ;
; N/A ; 226.19 MHz ( period = 4.421 ns ) ; counter24:u5|count[4] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 3.712 ns ;
; N/A ; 237.30 MHz ( period = 4.214 ns ) ; counter24:u5|count[0] ; counter24:u5|count[4] ; clk ; clk ; None ; None ; 3.505 ns ;
; N/A ; 246.61 MHz ( period = 4.055 ns ) ; counter24:u5|count[3] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 3.346 ns ;
; N/A ; 246.73 MHz ( period = 4.053 ns ) ; counter24:u5|count[3] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 3.344 ns ;
; N/A ; 247.04 MHz ( period = 4.048 ns ) ; counter24:u5|count[4] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 3.339 ns ;
; N/A ; 247.04 MHz ( period = 4.048 ns ) ; counter24:u5|count[5] ; counter24:u5|count[3] ; clk ; clk ; None ; None ; 3.339 ns ;
; N/A ; 247.22 MHz ( period = 4.045 ns ) ; counter24:u5|count[4] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 3.336 ns ;
; N/A ; 247.34 MHz ( period = 4.043 ns ) ; counter24:u5|count[4] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 3.334 ns ;
; N/A ; 257.20 MHz ( period = 3.888 ns ) ; counter24:u5|count[1] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 3.179 ns ;
; N/A ; 257.33 MHz ( period = 3.886 ns ) ; counter24:u5|count[1] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 3.177 ns ;
; N/A ; 261.92 MHz ( period = 3.818 ns ) ; counter6:u2|count[2] ; counter6:u2|c ; clk ; clk ; None ; None ; 3.109 ns ;
; N/A ; 264.34 MHz ( period = 3.783 ns ) ; counter10:u1|count[3] ; counter10:u1|count[1] ; clk ; clk ; None ; None ; 3.074 ns ;
; N/A ; 272.11 MHz ( period = 3.675 ns ) ; counter24:u5|count[5] ; counter24:u5|count[5] ; clk ; clk ; None ; None ; 2.966 ns ;
; N/A ; 272.33 MHz ( period = 3.672 ns ) ; counter24:u5|count[5] ; counter24:u5|count[1] ; clk ; clk ; None ; None ; 2.963 ns ;
; N/A ; 272.48 MHz ( period = 3.670 ns ) ; counter24:u5|count[5] ; counter24:u5|count[2] ; clk ; clk ; None ; None ; 2.961 ns ;
; N/A ; 276.01 MHz ( period = 3.623 ns ) ; counter6:u2|count[1] ; counter6:u2|c ; clk ; clk ; None ; None ; 2.914 ns ;
; N/A ; 292.91 MHz ( period = 3.414 ns ) ; counter10:u1|count[1] ; counter10:u1|c ; clk ; clk ; None ; None ; 2.705 ns ;
; N/A ; 298.06 MHz ( period = 3.355 ns ) ; counter6:u2|count[0] ; counter6:u2|c ; clk ; clk ; None ; None ; 2.646 ns ;
; N/A ; 302.21 MHz ( period = 3.309 ns ) ; counter10:u1|count[1] ; counter10:u1|count[3] ; clk ; clk ; None ; None ; 2.600 ns ;
; N/A ; 302.30 MHz ( period = 3.308 ns ) ; counter10:u1|count[1] ; counter10:u1|count[2] ; clk ; clk ; None ; None ; 2.599 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; counter10:u1|count[0] ; counter10:u1|c ; clk ; clk ; None ; None ; 2.520 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; counter10:u3|count[0] ; counter10:u3|c ; clk ; clk ; None ; None ; 2.475 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; counter10:u3|count[2] ; counter10:u3|count[1] ; clk ; clk ; None ; None ; 2.416 ns ;
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