adc0809.map.rpt

用CPLD/FPGA驱动ADC0809芯片的VHDL源程序

;     -- Register only                        ; 2     ;
;     -- Combinational with a register        ; 14    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 2     ;
;     -- 3 input functions                    ; 11    ;
;     -- 2 input functions                    ; 10    ;
;     -- 1 input functions                    ; 3     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 22    ;
;     -- arithmetic mode                      ; 6     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 16    ;
; Total logic cells in carry chains           ; 7     ;
; I/O pins                                    ; 28    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 16    ;
; Total fan-out                               ; 104   ;
; Average fan-out                             ; 1.86  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |ADC0809                   ; 28 (28)     ; 16           ; 0           ; 0            ; 0       ; 0         ; 0         ; 28   ; 0            ; 12 (12)      ; 2 (2)             ; 14 (14)          ; 7 (7)           ; 0 (0)      ; |ADC0809            ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |ADC0809|current_state                                                                                                                        ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name              ; current_state.st6 ; current_state.st5 ; current_state.st4 ; current_state.st3 ; current_state.st2 ; current_state.st1 ; current_state.st0 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; current_state.st0 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ;
; current_state.st1 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 1                 ;
; current_state.st2 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 1                 ;
; current_state.st3 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 1                 ;
; current_state.st4 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; current_state.st5 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; current_state.st6 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; regl[0]                                            ; current_state.st6   ; yes                    ;
; regl[1]                                            ; current_state.st6   ; yes                    ;
; regl[2]                                            ; current_state.st6   ; yes                    ;
; regl[3]                                            ; current_state.st6   ; yes                    ;
; regl[4]                                            ; current_state.st6   ; yes                    ;
; regl[5]                                            ; current_state.st6   ; yes                    ;
; regl[6]                                            ; current_state.st6   ; yes                    ;
; regl[7]                                            ; current_state.st6   ; yes                    ;
; Number of user-specified and inferred latches = 8  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 16    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 7     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Mon Nov 24 00:10:24 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adc0809 -c adc0809
Info: Found 2 design units, including 1 entities, in source file adc0809.vhd
    Info: Found design unit 1: ADC0809-behav
    Info: Found entity 1: ADC0809
Info: Elaborating entity "adc0809" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at adc0809.vhd(48): signal "d" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at adc0809.vhd(29): inferring latch(es) for signal or variable "regl", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "regl[0]" at adc0809.vhd(29)
Info (10041): Inferred latch for "regl[1]" at adc0809.vhd(29)
Info (10041): Inferred latch for "regl[2]" at adc0809.vhd(29)
Info (10041): Inferred latch for "regl[3]" at adc0809.vhd(29)
Info (10041): Inferred latch for "regl[4]" at adc0809.vhd(29)
Info (10041): Inferred latch for "regl[5]" at adc0809.vhd(29)
Info (10041): Inferred latch for "regl[6]" at adc0809.vhd(29)
Info (10041): Inferred latch for "regl[7]" at adc0809.vhd(29)
Info: State machine "|ADC0809|current_state" contains 7 states
Info: Selected Auto state machine encoding method for state machine "|ADC0809|current_state"
Info: Encoding result for state machine "|ADC0809|current_state"
    Info: Completed encoding using 7 state bits
        Info: Encoded state bit "current_state.st6"
        Info: Encoded state bit "current_state.st5"
        Info: Encoded state bit "current_state.st4"
        Info: Encoded state bit "current_state.st3"
        Info: Encoded state bit "current_state.st2"
        Info: Encoded state bit "current_state.st1"
        Info: Encoded state bit "current_state.st0"
    Info: State "|ADC0809|current_state.st0" uses code string "0000000"
    Info: State "|ADC0809|current_state.st1" uses code string "0000011"
    Info: State "|ADC0809|current_state.st2" uses code string "0000101"
    Info: State "|ADC0809|current_state.st3" uses code string "0001001"
    Info: State "|ADC0809|current_state.st4" uses code string "0010001"
    Info: State "|ADC0809|current_state.st5" uses code string "0100001"
    Info: State "|ADC0809|current_state.st6" uses code string "1000001"
Info: Implemented 56 device resources after synthesis - the final resource count might be different
    Info: Implemented 13 input pins
    Info: Implemented 15 output pins
    Info: Implemented 28 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 178 megabytes
    Info: Processing ended: Mon Nov 24 00:10:30 2008
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:04