adc0809.tan.qmsg

用CPLD/FPGA驱动ADC0809芯片的VHDL源程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[7\] regl\[7\] 14.660 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[7\]\" through register \"regl\[7\]\" is 14.660 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.671 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns current_state.st6 2 REG LC_X8_Y4_N5 10 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y4_N5; Fanout = 10; REG Node = 'current_state.st6'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk current_state.st6 } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.103 ns) + CELL(0.511 ns) 9.671 ns regl\[7\] 3 REG LC_X12_Y1_N2 1 " "Info: 3: + IC(5.103 ns) + CELL(0.511 ns) = 9.671 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'regl\[7\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { current_state.st6 regl[7] } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.968 ns ( 30.69 % ) " "Info: Total cell delay = 2.968 ns ( 30.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.703 ns ( 69.31 % ) " "Info: Total interconnect delay = 6.703 ns ( 69.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.671 ns" { clk current_state.st6 regl[7] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "9.671 ns" { clk {} clk~combout {} current_state.st6 {} regl[7] {} } { 0.000ns 0.000ns 1.600ns 5.103ns } { 0.000ns 1.163ns 1.294ns 0.511ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.989 ns + Longest register pin " "Info: + Longest register to pin delay is 4.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns regl\[7\] 1 REG LC_X12_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'regl\[7\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { regl[7] } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.667 ns) + CELL(2.322 ns) 4.989 ns q\[7\] 2 PIN PIN_74 0 " "Info: 2: + IC(2.667 ns) + CELL(2.322 ns) = 4.989 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'q\[7\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.989 ns" { regl[7] q[7] } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 46.54 % ) " "Info: Total cell delay = 2.322 ns ( 46.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.667 ns ( 53.46 % ) " "Info: Total interconnect delay = 2.667 ns ( 53.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.989 ns" { regl[7] q[7] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "4.989 ns" { regl[7] {} q[7] {} } { 0.000ns 2.667ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.671 ns" { clk current_state.st6 regl[7] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "9.671 ns" { clk {} clk~combout {} current_state.st6 {} regl[7] {} } { 0.000ns 0.000ns 1.600ns 5.103ns } { 0.000ns 1.163ns 1.294ns 0.511ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.989 ns" { regl[7] q[7] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "4.989 ns" { regl[7] {} q[7] {} } { 0.000ns 2.667ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "abc_in\[0\] abc_out\[0\] 6.414 ns Longest " "Info: Longest tpd from source pin \"abc_in\[0\]\" to destination pin \"abc_out\[0\]\" is 6.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns abc_in\[0\] 1 PIN PIN_92 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_92; Fanout = 1; PIN Node = 'abc_in\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { abc_in[0] } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.960 ns) + CELL(2.322 ns) 6.414 ns abc_out\[0\] 2 PIN PIN_95 0 " "Info: 2: + IC(2.960 ns) + CELL(2.322 ns) = 6.414 ns; Loc. = PIN_95; Fanout = 0; PIN Node = 'abc_out\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.282 ns" { abc_in[0] abc_out[0] } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.454 ns ( 53.85 % ) " "Info: Total cell delay = 3.454 ns ( 53.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.960 ns ( 46.15 % ) " "Info: Total interconnect delay = 2.960 ns ( 46.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.414 ns" { abc_in[0] abc_out[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "6.414 ns" { abc_in[0] {} abc_in[0]~combout {} abc_out[0] {} } { 0.000ns 0.000ns 2.960ns } { 0.000ns 1.132ns 2.322ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "regl\[7\] d\[7\] clk 4.944 ns register " "Info: th for register \"regl\[7\]\" (data pin = \"d\[7\]\", clock pin = \"clk\") is 4.944 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.671 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns current_state.st6 2 REG LC_X8_Y4_N5 10 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y4_N5; Fanout = 10; REG Node = 'current_state.st6'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk current_state.st6 } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.103 ns) + CELL(0.511 ns) 9.671 ns regl\[7\] 3 REG LC_X12_Y1_N2 1 " "Info: 3: + IC(5.103 ns) + CELL(0.511 ns) = 9.671 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'regl\[7\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { current_state.st6 regl[7] } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.968 ns ( 30.69 % ) " "Info: Total cell delay = 2.968 ns ( 30.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.703 ns ( 69.31 % ) " "Info: Total interconnect delay = 6.703 ns ( 69.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.671 ns" { clk current_state.st6 regl[7] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "9.671 ns" { clk {} clk~combout {} current_state.st6 {} regl[7] {} } { 0.000ns 0.000ns 1.600ns 5.103ns } { 0.000ns 1.163ns 1.294ns 0.511ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.727 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.727 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns d\[7\] 1 PIN PIN_52 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_52; Fanout = 1; PIN Node = 'd\[7\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[7] } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.855 ns) + CELL(0.740 ns) 4.727 ns regl\[7\] 2 REG LC_X12_Y1_N2 1 " "Info: 2: + IC(2.855 ns) + CELL(0.740 ns) = 4.727 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'regl\[7\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.595 ns" { d[7] regl[7] } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.872 ns ( 39.60 % ) " "Info: Total cell delay = 1.872 ns ( 39.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.855 ns ( 60.40 % ) " "Info: Total interconnect delay = 2.855 ns ( 60.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.727 ns" { d[7] regl[7] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "4.727 ns" { d[7] {} d[7]~combout {} regl[7] {} } { 0.000ns 0.000ns 2.855ns } { 0.000ns 1.132ns 0.740ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.671 ns" { clk current_state.st6 regl[7] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "9.671 ns" { clk {} clk~combout {} current_state.st6 {} regl[7] {} } { 0.000ns 0.000ns 1.600ns 5.103ns } { 0.000ns 1.163ns 1.294ns 0.511ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.727 ns" { d[7] regl[7] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "4.727 ns" { d[7] {} d[7]~combout {} regl[7] {} } { 0.000ns 0.000ns 2.855ns } { 0.000ns 1.132ns 0.740ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 11 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "121 " "Info: Peak virtual memory: 121 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 24 00:10:48 2008 " "Info: Processing ended: Mon Nov 24 00:10:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}