adc0809.tan.qmsg

用CPLD/FPGA驱动ADC0809芯片的VHDL源程序

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[0\] " "Warning: Node \"regl\[0\]\" is a latch" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[1\] " "Warning: Node \"regl\[1\]\" is a latch" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[2\] " "Warning: Node \"regl\[2\]\" is a latch" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[3\] " "Warning: Node \"regl\[3\]\" is a latch" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[4\] " "Warning: Node \"regl\[4\]\" is a latch" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[5\] " "Warning: Node \"regl\[5\]\" is a latch" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[6\] " "Warning: Node \"regl\[6\]\" is a latch" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "regl\[7\] " "Warning: Node \"regl\[7\]\" is a latch" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 29 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 13 -1 0 } } { "d:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "current_state.st6 " "Info: Detected ripple clock \"current_state.st6\" as buffer" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 23 -1 0 } } { "d:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "current_state.st6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register qq\[1\] register current_state.st2 151.01 MHz 6.622 ns Internal " "Info: Clock \"clk\" has Internal fmax of 151.01 MHz between source register \"qq\[1\]\" and destination register \"current_state.st2\" (period= 6.622 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.913 ns + Longest register register " "Info: + Longest register to register delay is 5.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qq\[1\] 1 REG LC_X6_Y4_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y4_N1; Fanout = 4; REG Node = 'qq\[1\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { qq[1] } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.740 ns) 1.669 ns Equal0~64 2 COMB LC_X6_Y4_N0 1 " "Info: 2: + IC(0.929 ns) + CELL(0.740 ns) = 1.669 ns; Loc. = LC_X6_Y4_N0; Fanout = 1; COMB Node = 'Equal0~64'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.669 ns" { qq[1] Equal0~64 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.781 ns) + CELL(0.511 ns) 2.961 ns Equal0~66 3 COMB LC_X6_Y4_N9 8 " "Info: 3: + IC(0.781 ns) + CELL(0.511 ns) = 2.961 ns; Loc. = LC_X6_Y4_N9; Fanout = 8; COMB Node = 'Equal0~66'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.292 ns" { Equal0~64 Equal0~66 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.709 ns) + CELL(1.243 ns) 5.913 ns current_state.st2 4 REG LC_X8_Y4_N7 2 " "Info: 4: + IC(1.709 ns) + CELL(1.243 ns) = 5.913 ns; Loc. = LC_X8_Y4_N7; Fanout = 2; REG Node = 'current_state.st2'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.952 ns" { Equal0~66 current_state.st2 } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.494 ns ( 42.18 % ) " "Info: Total cell delay = 2.494 ns ( 42.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.419 ns ( 57.82 % ) " "Info: Total interconnect delay = 3.419 ns ( 57.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.913 ns" { qq[1] Equal0~64 Equal0~66 current_state.st2 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.913 ns" { qq[1] {} Equal0~64 {} Equal0~66 {} current_state.st2 {} } { 0.000ns 0.929ns 0.781ns 1.709ns } { 0.000ns 0.740ns 0.511ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.681 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns current_state.st2 2 REG LC_X8_Y4_N7 2 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X8_Y4_N7; Fanout = 2; REG Node = 'current_state.st2'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk current_state.st2 } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk current_state.st2 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} current_state.st2 {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.681 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns qq\[1\] 2 REG LC_X6_Y4_N1 4 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X6_Y4_N1; Fanout = 4; REG Node = 'qq\[1\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk qq[1] } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk qq[1] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} qq[1] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk current_state.st2 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} current_state.st2 {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk qq[1] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} qq[1] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.913 ns" { qq[1] Equal0~64 Equal0~66 current_state.st2 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.913 ns" { qq[1] {} Equal0~64 {} Equal0~66 {} current_state.st2 {} } { 0.000ns 0.929ns 0.781ns 1.709ns } { 0.000ns 0.740ns 0.511ns 1.243ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk current_state.st2 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} current_state.st2 {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk qq[1] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} qq[1] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.st5 eoc clk 2.047 ns register " "Info: tsu for register \"current_state.st5\" (data pin = \"eoc\", clock pin = \"clk\") is 2.047 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.395 ns + Longest pin register " "Info: + Longest pin to register delay is 5.395 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns eoc 1 PIN PIN_40 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 3; PIN Node = 'eoc'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoc } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.202 ns) + CELL(1.061 ns) 5.395 ns current_state.st5 2 REG LC_X8_Y4_N1 2 " "Info: 2: + IC(3.202 ns) + CELL(1.061 ns) = 5.395 ns; Loc. = LC_X8_Y4_N1; Fanout = 2; REG Node = 'current_state.st5'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.263 ns" { eoc current_state.st5 } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 40.65 % ) " "Info: Total cell delay = 2.193 ns ( 40.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.202 ns ( 59.35 % ) " "Info: Total interconnect delay = 3.202 ns ( 59.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.395 ns" { eoc current_state.st5 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.395 ns" { eoc {} eoc~combout {} current_state.st5 {} } { 0.000ns 0.000ns 3.202ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.681 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns current_state.st5 2 REG LC_X8_Y4_N1 2 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X8_Y4_N1; Fanout = 2; REG Node = 'current_state.st5'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk current_state.st5 } "NODE_NAME" } } { "adc0809.vhd" "" { Text "E:/CPLD/ADC0809/adc0809.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk current_state.st5 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} current_state.st5 {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.395 ns" { eoc current_state.st5 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.395 ns" { eoc {} eoc~combout {} current_state.st5 {} } { 0.000ns 0.000ns 3.202ns } { 0.000ns 1.132ns 1.061ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk current_state.st5 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} current_state.st5 {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}