adc0809.fit.rpt

用CPLD/FPGA驱动ADC0809芯片的VHDL源程序

; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:10;1:1    ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:11        ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:11        ;
; LEs in Chains - Fit Attempt 1                                                  ; 7           ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0           ;
; LABs with Chains - Fit Attempt 1                                               ; 1           ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0           ;
; Time - Fit Attempt 1                                                           ; 0           ;
+--------------------------------------------------------------------------------+-------------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+------------------------------------+--------+
; Name                               ; Value  ;
+------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1   ; ff     ;
; Early Wire Use - Fit Attempt 1     ; 1      ;
; Early Slack - Fit Attempt 1        ; -16083 ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff     ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff     ;
; Mid Wire Use - Fit Attempt 1       ; 2      ;
; Mid Slack - Fit Attempt 1          ; -13762 ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff     ;
; Late Wire Use - Fit Attempt 1      ; 2      ;
; Late Slack - Fit Attempt 1         ; -13762 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000  ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff     ;
; Time - Fit Attempt 1               ; 0      ;
+------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1      ; 1      ;
; Peak Regional Wire - Fit Attempt 1  ; 1      ;
; Early Slack - Fit Attempt 1         ; -14029 ;
; Mid Slack - Fit Attempt 1           ; -14029 ;
; Late Slack - Fit Attempt 1          ; -14029 ;
; Late Wire Use - Fit Attempt 1       ; 2      ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.010  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Mon Nov 24 00:10:32 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adc0809 -c adc0809
Info: Selected device EPM570T100C5 for design "adc0809"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100C5 is compatible
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM240T100A5 is compatible
    Info: Device EPM570T100I5 is compatible
    Info: Device EPM570T100A5 is compatible
Warning: No exact pin location assignment(s) for 28 pins of 28 total pins
    Info: Pin clk1 not assigned to an exact location on the device
    Info: Pin start not assigned to an exact location on the device
    Info: Pin ale not assigned to an exact location on the device
    Info: Pin en not assigned to an exact location on the device
    Info: Pin abc_out[0] not assigned to an exact location on the device
    Info: Pin abc_out[1] not assigned to an exact location on the device
    Info: Pin abc_out[2] not assigned to an exact location on the device
    Info: Pin q[0] not assigned to an exact location on the device
    Info: Pin q[1] not assigned to an exact location on the device
    Info: Pin q[2] not assigned to an exact location on the device
    Info: Pin q[3] not assigned to an exact location on the device
    Info: Pin q[4] not assigned to an exact location on the device
    Info: Pin q[5] not assigned to an exact location on the device
    Info: Pin q[6] not assigned to an exact location on the device
    Info: Pin q[7] not assigned to an exact location on the device
    Info: Pin abc_in[0] not assigned to an exact location on the device
    Info: Pin abc_in[1] not assigned to an exact location on the device
    Info: Pin abc_in[2] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin eoc not assigned to an exact location on the device
    Info: Pin d[0] not assigned to an exact location on the device
    Info: Pin d[1] not assigned to an exact location on the device
    Info: Pin d[2] not assigned to an exact location on the device
    Info: Pin d[3] not assigned to an exact location on the device
    Info: Pin d[4] not assigned to an exact location on the device
    Info: Pin d[5] not assigned to an exact location on the device
    Info: Pin d[6] not assigned to an exact location on the device
    Info: Pin d[7] not assigned to an exact location on the device
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal "current_state.st6" to use Global clock
    Info: Destination "en~0" may be non-global or may not use global clock
    Info: Destination "current_state.st0" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 27 (unused VREF, 3.3V VCCIO, 12 input, 15 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  35 pins available
        Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  40 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 4.770 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y1; Fanout = 1; REG Node = 'regl[7]'
    Info: 2: + IC(2.448 ns) + CELL(2.322 ns) = 4.770 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'q[7]'
    Info: Total cell delay = 2.322 ns ( 48.68 % )
    Info: Total interconnect delay = 2.448 ns ( 51.32 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources
    Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X0_Y0 to location X13_Y8
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file E:/CPLD/ADC0809/adc0809.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 179 megabytes
    Info: Processing ended: Mon Nov 24 00:10:39 2008
    Info: Elapsed time: 00:00:07
    Info: Total CPU time (on all processors): 00:00:03


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/CPLD/ADC0809/adc0809.fit.smsg.