adc0809.tan.rpt

用CPLD/FPGA驱动ADC0809芯片的VHDL源程序

+----------------------------------------------------------------------+
; tpd                                                                  ;
+-------+-------------------+-----------------+-----------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From      ; To         ;
+-------+-------------------+-----------------+-----------+------------+
; N/A   ; None              ; 6.414 ns        ; abc_in[0] ; abc_out[0] ;
; N/A   ; None              ; 4.839 ns        ; abc_in[2] ; abc_out[2] ;
; N/A   ; None              ; 4.788 ns        ; abc_in[1] ; abc_out[1] ;
+-------+-------------------+-----------------+-----------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; 4.944 ns  ; d[7] ; regl[7]           ; clk      ;
; N/A           ; None        ; 4.291 ns  ; d[1] ; regl[1]           ; clk      ;
; N/A           ; None        ; 4.039 ns  ; d[0] ; regl[0]           ; clk      ;
; N/A           ; None        ; 4.038 ns  ; d[2] ; regl[2]           ; clk      ;
; N/A           ; None        ; 4.003 ns  ; d[5] ; regl[5]           ; clk      ;
; N/A           ; None        ; 3.655 ns  ; d[4] ; regl[4]           ; clk      ;
; N/A           ; None        ; 3.518 ns  ; d[6] ; regl[6]           ; clk      ;
; N/A           ; None        ; 3.506 ns  ; d[3] ; regl[3]           ; clk      ;
; N/A           ; None        ; -1.135 ns ; eoc  ; current_state.st3 ; clk      ;
; N/A           ; None        ; -1.150 ns ; eoc  ; current_state.st4 ; clk      ;
; N/A           ; None        ; -1.493 ns ; eoc  ; current_state.st5 ; clk      ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Mon Nov 24 00:10:46 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adc0809 -c adc0809
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "regl[0]" is a latch
    Warning: Node "regl[1]" is a latch
    Warning: Node "regl[2]" is a latch
    Warning: Node "regl[3]" is a latch
    Warning: Node "regl[4]" is a latch
    Warning: Node "regl[5]" is a latch
    Warning: Node "regl[6]" is a latch
    Warning: Node "regl[7]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "current_state.st6" as buffer
Info: Clock "clk" has Internal fmax of 151.01 MHz between source register "qq[1]" and destination register "current_state.st2" (period= 6.622 ns)
    Info: + Longest register to register delay is 5.913 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y4_N1; Fanout = 4; REG Node = 'qq[1]'
        Info: 2: + IC(0.929 ns) + CELL(0.740 ns) = 1.669 ns; Loc. = LC_X6_Y4_N0; Fanout = 1; COMB Node = 'Equal0~64'
        Info: 3: + IC(0.781 ns) + CELL(0.511 ns) = 2.961 ns; Loc. = LC_X6_Y4_N9; Fanout = 8; COMB Node = 'Equal0~66'
        Info: 4: + IC(1.709 ns) + CELL(1.243 ns) = 5.913 ns; Loc. = LC_X8_Y4_N7; Fanout = 2; REG Node = 'current_state.st2'
        Info: Total cell delay = 2.494 ns ( 42.18 % )
        Info: Total interconnect delay = 3.419 ns ( 57.82 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.681 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X8_Y4_N7; Fanout = 2; REG Node = 'current_state.st2'
            Info: Total cell delay = 2.081 ns ( 56.53 % )
            Info: Total interconnect delay = 1.600 ns ( 43.47 % )
        Info: - Longest clock path from clock "clk" to source register is 3.681 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X6_Y4_N1; Fanout = 4; REG Node = 'qq[1]'
            Info: Total cell delay = 2.081 ns ( 56.53 % )
            Info: Total interconnect delay = 1.600 ns ( 43.47 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "current_state.st5" (data pin = "eoc", clock pin = "clk") is 2.047 ns
    Info: + Longest pin to register delay is 5.395 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 3; PIN Node = 'eoc'
        Info: 2: + IC(3.202 ns) + CELL(1.061 ns) = 5.395 ns; Loc. = LC_X8_Y4_N1; Fanout = 2; REG Node = 'current_state.st5'
        Info: Total cell delay = 2.193 ns ( 40.65 % )
        Info: Total interconnect delay = 3.202 ns ( 59.35 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.681 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X8_Y4_N1; Fanout = 2; REG Node = 'current_state.st5'
        Info: Total cell delay = 2.081 ns ( 56.53 % )
        Info: Total interconnect delay = 1.600 ns ( 43.47 % )
Info: tco from clock "clk" to destination pin "q[7]" through register "regl[7]" is 14.660 ns
    Info: + Longest clock path from clock "clk" to source register is 9.671 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y4_N5; Fanout = 10; REG Node = 'current_state.st6'
        Info: 3: + IC(5.103 ns) + CELL(0.511 ns) = 9.671 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'regl[7]'
        Info: Total cell delay = 2.968 ns ( 30.69 % )
        Info: Total interconnect delay = 6.703 ns ( 69.31 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 4.989 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'regl[7]'
        Info: 2: + IC(2.667 ns) + CELL(2.322 ns) = 4.989 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'q[7]'
        Info: Total cell delay = 2.322 ns ( 46.54 % )
        Info: Total interconnect delay = 2.667 ns ( 53.46 % )
Info: Longest tpd from source pin "abc_in[0]" to destination pin "abc_out[0]" is 6.414 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_92; Fanout = 1; PIN Node = 'abc_in[0]'
    Info: 2: + IC(2.960 ns) + CELL(2.322 ns) = 6.414 ns; Loc. = PIN_95; Fanout = 0; PIN Node = 'abc_out[0]'
    Info: Total cell delay = 3.454 ns ( 53.85 % )
    Info: Total interconnect delay = 2.960 ns ( 46.15 % )
Info: th for register "regl[7]" (data pin = "d[7]", clock pin = "clk") is 4.944 ns
    Info: + Longest clock path from clock "clk" to destination register is 9.671 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y4_N5; Fanout = 10; REG Node = 'current_state.st6'
        Info: 3: + IC(5.103 ns) + CELL(0.511 ns) = 9.671 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'regl[7]'
        Info: Total cell delay = 2.968 ns ( 30.69 % )
        Info: Total interconnect delay = 6.703 ns ( 69.31 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 4.727 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_52; Fanout = 1; PIN Node = 'd[7]'
        Info: 2: + IC(2.855 ns) + CELL(0.740 ns) = 4.727 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'regl[7]'
        Info: Total cell delay = 1.872 ns ( 39.60 % )
        Info: Total interconnect delay = 2.855 ns ( 60.40 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 11 warnings
    Info: Peak virtual memory: 121 megabytes
    Info: Processing ended: Mon Nov 24 00:10:48 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02