moore.fit.rpt

来自「moore状态机用VHDL语言进行实现」· RPT 代码 · 共 655 行 · 第 1/4 页

+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+-----------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                   ;
+--------------------------------------------------------------------------------+--------+
; Name                                                                           ; Value  ;
+--------------------------------------------------------------------------------+--------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff     ;
; Mid Wire Use - Fit Attempt 1                                                   ; 1      ;
; Mid Slack - Fit Attempt 1                                                      ; -11123 ;
; Internal Atom Count - Fit Attempt 1                                            ; 6      ;
; LE/ALM Count - Fit Attempt 1                                                   ; 6      ;
; LAB Count - Fit Attempt 1                                                      ; 1      ;
; Outputs per Lab - Fit Attempt 1                                                ; 2.000  ;
; Inputs per LAB - Fit Attempt 1                                                 ; 2.000  ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 2.000  ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:1    ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:1    ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:1    ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:1    ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 1:1    ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 1:1    ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:1    ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:1    ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:1    ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 2:1    ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 1:1    ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:1    ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 1:1    ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:1    ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 1:1    ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:1    ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:1    ;
; LEs in Chains - Fit Attempt 1                                                  ; 0      ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0      ;
; LABs with Chains - Fit Attempt 1                                               ; 0      ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0      ;
; Time - Fit Attempt 1                                                           ; 0      ;
+--------------------------------------------------------------------------------+--------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+------------------------------------+--------+
; Name                               ; Value  ;
+------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1   ; ff     ;
; Early Wire Use - Fit Attempt 1     ; 0      ;
; Early Slack - Fit Attempt 1        ; -9410  ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff     ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff     ;
; Mid Wire Use - Fit Attempt 1       ; 1      ;
; Mid Slack - Fit Attempt 1          ; -10045 ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff     ;
; Late Wire Use - Fit Attempt 1      ; 1      ;
; Late Slack - Fit Attempt 1         ; -10045 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000  ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff     ;
; Time - Fit Attempt 1               ; 0      ;
+------------------------------------+--------+


+--------------------------------------------+
; Advanced Data - Routing                    ;
+------------------------------------+-------+
; Name                               ; Value ;
+------------------------------------+-------+
; Early Wire Use - Fit Attempt 1     ; 0     ;
; Peak Regional Wire - Fit Attempt 1 ; 0     ;
; Early Slack - Fit Attempt 1        ; -9102 ;
; Mid Slack - Fit Attempt 1          ; -9392 ;
; Late Slack - Fit Attempt 1         ; -9392 ;
; Late Wire Use - Fit Attempt 1      ; 1     ;
; Time - Fit Attempt 1               ; 0     ;
+------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Nov 06 17:02:42 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off moore -c moore
Info: Selected device EPM240GT100C5 for design "moore"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240GT100I5 is compatible
    Info: Device EPM570GT100C5 is compatible
    Info: Device EPM570GT100I5 is compatible
Warning: No exact pin location assignment(s) for 6 pins of 6 total pins
    Info: Pin oe not assigned to an exact location on the device
    Info: Pin we not assigned to an exact location on the device
    Info: Pin read_write not assigned to an exact location on the device
    Info: Pin ready not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin reset not assigned to an exact location on the device
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 14
Info: Automatically promoted signal "reset" to use Global clock in PIN 12
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 4 (unused VREF, 3.3V VCCIO, 2 input, 2 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  36 pins available
        Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:03
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 6.048 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y2; Fanout = 4; REG Node = 'present_state.idle'
    Info: 2: + IC(1.156 ns) + CELL(0.200 ns) = 1.356 ns; Loc. = LAB_X4_Y2; Fanout = 1; COMB Node = 'we~0'
    Info: 3: + IC(2.370 ns) + CELL(2.322 ns) = 6.048 ns; Loc. = PIN_82; Fanout = 0; PIN Node = 'we'
    Info: Total cell delay = 2.522 ns ( 41.70 % )
    Info: Total interconnect delay = 3.526 ns ( 58.30 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
    Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file F:/QuartusII8.0work/moore/moore.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 170 megabytes
    Info: Processing ended: Thu Nov 06 17:02:55 2008
    Info: Elapsed time: 00:00:13
    Info: Total CPU time (on all processors): 00:00:02


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/QuartusII8.0work/moore/moore.fit.smsg.