decoder_38.vhd

采用VHDL语言编写8线-3线优先编码器

library ieee;
use ieee.std_logic_1164.all;

entity decoder_38 is
   port(A0,A1,A2:in bit;
             s1,s2,s3:in bit;
             y0,y1,y2,y3,y4,y5,y6,y7:out bit);
end decoder_38;

architecture rt1 of decoder_38 is
   signal s:bit;
   signal A:bit_vector(2 downto 0);
   signal y:bit_vector(7 downto 0);
begin
   process(A,s1,s2,s3)
   begin
     s<=s2 or s3;
     A<=A2&A1&A0;
        if s1='0' then
        y<="11111111";
        elsif s='1' then
        y<="11111111";
        else
        case A is
        when "000"=>y<="11111110";
        when "001"=>y<="11111101";
        when "010"=>y<="11111011";
        when "011"=>y<="11110111";
        when "100"=>y<="11101111";
        when "101"=>y<="11011111";
        when "110"=>y<="10111111";
        when others=>y<="01111111";
        end case;
        end if;
    end process;
    y0<=y(0);
    y1<=y(1);
    y2<=y(2);
    y3<=y(3);
    y4<=y(4);
    y5<=y(5);
    y6<=y(6);
    y7<=y(7);
    end rt1;