decoder_38.rpt

采用VHDL语言编写8线-3线优先编码器

Device-Specific Information:           f:\vhdl\exp3\decoder_3_8\decoder_38.rpt
decoder_38

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
s1       : INPUT;
s2       : INPUT;
s3       : INPUT;

-- Node name is 'y0' 
-- Equation name is 'y0', type is output 
y0       =  _LC8_D8;

-- Node name is 'y1' 
-- Equation name is 'y1', type is output 
y1       =  _LC6_D8;

-- Node name is 'y2' 
-- Equation name is 'y2', type is output 
y2       =  _LC2_D8;

-- Node name is 'y3' 
-- Equation name is 'y3', type is output 
y3       =  _LC4_D8;

-- Node name is 'y4' 
-- Equation name is 'y4', type is output 
y4       =  _LC1_D8;

-- Node name is 'y5' 
-- Equation name is 'y5', type is output 
y5       =  _LC3_D8;

-- Node name is 'y6' 
-- Equation name is 'y6', type is output 
y6       =  _LC7_D8;

-- Node name is 'y7' 
-- Equation name is 'y7', type is output 
y7       =  _LC5_D8;

-- Node name is ':570' 
-- Equation name is '_LC5_D8', type is buried 
_LC5_D8  = LCELL( _EQ001);
  _EQ001 =  _LC1_D24
         # !A1 &  A2
         # !A0 &  A2
         #  A1 & !A2
         # !A0 & !A1
         #  A0 & !A2;

-- Node name is ':579' 
-- Equation name is '_LC7_D8', type is buried 
_LC7_D8  = LCELL( _EQ002);
  _EQ002 =  _LC1_D24
         # !A1
         #  A0
         # !A2;

-- Node name is ':588' 
-- Equation name is '_LC3_D8', type is buried 
_LC3_D8  = LCELL( _EQ003);
  _EQ003 =  _LC1_D24
         #  A1
         # !A0
         # !A2;

-- Node name is ':597' 
-- Equation name is '_LC1_D8', type is buried 
_LC1_D8  = LCELL( _EQ004);
  _EQ004 =  _LC1_D24
         #  A1
         #  A0
         # !A2;

-- Node name is '~606~1' 
-- Equation name is '~606~1', location is LC1_D24, type is buried.
-- synthesized logic cell 
_LC1_D24 = LCELL( _EQ005);
  _EQ005 =  s2
         #  s3
         # !s1;

-- Node name is ':606' 
-- Equation name is '_LC4_D8', type is buried 
_LC4_D8  = LCELL( _EQ006);
  _EQ006 = !A1
         # !A0
         #  A2
         #  _LC1_D24;

-- Node name is ':615' 
-- Equation name is '_LC2_D8', type is buried 
_LC2_D8  = LCELL( _EQ007);
  _EQ007 = !A1
         #  A0
         #  A2
         #  _LC1_D24;

-- Node name is ':624' 
-- Equation name is '_LC6_D8', type is buried 
_LC6_D8  = LCELL( _EQ008);
  _EQ008 =  A1
         # !A0
         #  A2
         #  _LC1_D24;

-- Node name is ':633' 
-- Equation name is '_LC8_D8', type is buried 
_LC8_D8  = LCELL( _EQ009);
  _EQ009 =  A1
         #  A0
         #  A2
         #  _LC1_D24;



Project Information                    f:\vhdl\exp3\decoder_3_8\decoder_38.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 50,972K