bmq.rpt

采用VHDL语言编写的二-十进制编码器

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Device-Specific Information:                 f:\vhdl\exp3\decoder_2_10\bmq.rpt
bmq

** EQUATIONS **

i0       : INPUT;
i1       : INPUT;
i2       : INPUT;
i3       : INPUT;
i4       : INPUT;
i5       : INPUT;
i6       : INPUT;
i7       : INPUT;
i8       : INPUT;

-- Node name is 'y0' 
-- Equation name is 'y0', type is output 
y0       =  _LC4_B49;

-- Node name is 'y1' 
-- Equation name is 'y1', type is output 
y1       =  _LC6_B49;

-- Node name is 'y2' 
-- Equation name is 'y2', type is output 
y2       =  _LC8_B49;

-- Node name is 'y3' 
-- Equation name is 'y3', type is output 
y3       =  _LC1_C32;

-- Node name is ':424' 
-- Equation name is '_LC1_C32', type is buried 
_LC1_C32 = LCELL( _EQ001);
  _EQ001 =  i7 &  i8;

-- Node name is ':426' 
-- Equation name is '_LC3_B49', type is buried 
!_LC3_B49 = _LC3_B49~NOT;
_LC3_B49~NOT = LCELL( _EQ002);
  _EQ002 = !i8
         # !i7;

-- Node name is '~456~1' 
-- Equation name is '~456~1', location is LC5_B49, type is buried.
-- synthesized logic cell 
!_LC5_B49 = _LC5_B49~NOT;
_LC5_B49~NOT = LCELL( _EQ003);
  _EQ003 = !i4
         # !i3;

-- Node name is ':457' 
-- Equation name is '_LC8_B49', type is buried 
_LC8_B49 = LCELL( _EQ004);
  _EQ004 =  i5 &  i6 &  _LC5_B49
         # !_LC3_B49;

-- Node name is ':478' 
-- Equation name is '_LC7_B49', type is buried 
_LC7_B49 = LCELL( _EQ005);
  _EQ005 = !_LC5_B49
         #  i1 &  i2;

-- Node name is ':490' 
-- Equation name is '_LC6_B49', type is buried 
_LC6_B49 = LCELL( _EQ006);
  _EQ006 = !_LC3_B49
         #  i5 &  i6 &  _LC7_B49;

-- Node name is ':510' 
-- Equation name is '_LC1_B49', type is buried 
_LC1_B49 = LCELL( _EQ007);
  _EQ007 = !i1 &  i2
         #  i0 &  i2;

-- Node name is ':514' 
-- Equation name is '_LC2_B49', type is buried 
_LC2_B49 = LCELL( _EQ008);
  _EQ008 = !i5
         # !i3 &  i4
         #  i4 &  _LC1_B49;

-- Node name is ':523' 
-- Equation name is '_LC4_B49', type is buried 
_LC4_B49 = LCELL( _EQ009);
  _EQ009 = !i7 &  i8
         #  i6 &  i8 &  _LC2_B49;



Project Information                          f:\vhdl\exp3\decoder_2_10\bmq.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 52,704K