bmq.vhd

采用VHDL语言编写的二-十进制编码器

library ieee;
use ieee.std_logic_1164.all;

entity bmq is
  port(i:in std_logic_vector(8 downto 0);y:out std_logic_vector(3 downto 0));
end bmq;
architecture rtl of bmq is
begin
process(i)
begin
if i(8)='0'then
y<="0110";
elsif i(7)='0'then
y<="0111";
elsif i(6)='0'then
y<="1000";
elsif i(5)='0'then
y<="1001";
elsif i(4)='0'then
y<="1010";
elsif i(3)='0'then
y<="1011";
elsif i(2)='0'then
y<="1100";
elsif i(1)='0'then
y<="1101";
elsif i(0)='0'then
y<="1110";
elsif i="111111111"then
y<="1111";
end if;
end process;
end rtl;