bid_shift_reg.vhd

VHDL语言编写

library ieee;
use ieee.std_logic_1164.all;
package shift_type is
subtype std4 is std_logic_vector(3 downto 0);
end shift_type;
library ieee;
use ieee.std_logic_1164.all;
use work.shift_type.all;
entity bid_shift_reg is
  port(din:in std4;
        clk,load,left_right:in std_logic;
        dout:buffer std4);
end bid_shift_reg;
architecture rt1 of bid_shift_reg is
signal shift_val:std4;
begin
   nxt:process(load,left_right,din,dout)
   begin
     if load='1' then
        shift_val<=din;
     elsif left_right='0' then
        shift_val(2 downto 0)<=dout(3 downto 1);
        shift_val(3)<='0';
     else
        shift_val(3 downto 1)<=dout(2 downto 0);
        shift_val(0)<='0';
     end if;
end process nxt;
current:process(clk)
begin
      if clk'event and clk='1' then
          dout<=shift_val;
      end if;
end process current;
end rt1;