📄 bid_shift_reg.rpt
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Device-Specific Information: f:\vhdl\exp7\bid_shift_reg\bid_shift_reg.rpt
bid_shift_reg
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: f:\vhdl\exp7\bid_shift_reg\bid_shift_reg.rpt
bid_shift_reg
** EQUATIONS **
clk : INPUT;
din0 : INPUT;
din1 : INPUT;
din2 : INPUT;
din3 : INPUT;
left_right : INPUT;
load : INPUT;
-- Node name is 'dout0'
-- Equation name is 'dout0', type is output
dout0 = _LC2_F49;
-- Node name is 'dout1'
-- Equation name is 'dout1', type is output
dout1 = _LC1_F48;
-- Node name is 'dout2'
-- Equation name is 'dout2', type is output
dout2 = _LC4_F48;
-- Node name is 'dout3'
-- Equation name is 'dout3', type is output
dout3 = _LC1_F46;
-- Node name is ':8'
-- Equation name is '_LC1_F46', type is buried
_LC1_F46 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC4_F48 & left_right & !load
# din3 & load;
-- Node name is ':10'
-- Equation name is '_LC4_F48', type is buried
_LC4_F48 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC3_F48 & !load
# din2 & load;
-- Node name is ':12'
-- Equation name is '_LC1_F48', type is buried
_LC1_F48 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC2_F48 & !load
# din1 & load;
-- Node name is ':14'
-- Equation name is '_LC2_F49', type is buried
_LC2_F49 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC1_F48 & !left_right & !load
# din0 & load;
-- Node name is ':200'
-- Equation name is '_LC3_F48', type is buried
_LC3_F48 = LCELL( _EQ005);
_EQ005 = _LC1_F48 & left_right
# _LC1_F46 & !left_right;
-- Node name is ':209'
-- Equation name is '_LC2_F48', type is buried
_LC2_F48 = LCELL( _EQ006);
_EQ006 = _LC4_F48 & !left_right
# _LC2_F49 & left_right;
Project Information f:\vhdl\exp7\bid_shift_reg\bid_shift_reg.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 55,690K
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