bid_shift_reg.fit

VHDL语言编写

-- MAX+plus II Compiler Fit File      
-- Version 10.0 9/14/2000             
-- Compiled: 05/16/2008 11:07:19      

-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "bid_shift_reg"
BEGIN

    DEVICE = "EP1K100QC208-3";

    "clk"                          : INPUT_PIN  = 79     ;
    "din0"                         : INPUT_PIN  = 64     ;
    "din1"                         : INPUT_PIN  = 65     ;
    "din2"                         : INPUT_PIN  = 67     ;
    "din3"                         : INPUT_PIN  = 68     ;
    "left_right"                   : INPUT_PIN  = 69     ;
    "load"                         : INPUT_PIN  = 70     ;
    "dout0"                        : OUTPUT_PIN = 205    ;
    "dout1"                        : OUTPUT_PIN = 203    ;
    "dout2"                        : OUTPUT_PIN = 202    ;
    "dout3"                        : OUTPUT_PIN = 200    ;
    ":8"                           : LOCATION   = LC1_F46;
    ":10"                          : LOCATION   = LC4_F48;
    ":12"                          : LOCATION   = LC1_F48;
    ":14"                          : LOCATION   = LC2_F49;
    ":200"                         : LOCATION   = LC3_F48;
    ":209"                         : LOCATION   = LC2_F48;

END;

INTERNAL_INFO "bid_shift_reg"
BEGIN
	DEVICE = EP1K100QC208-3;
    OD5P79  : LORAX = "1:FB5->LC1_F46,->LC4_F48,->LC1_F48,->LC2_F49|";
    OV3C34P64 : LORAX = "1:V18C34,HHR92R5,PA23R5C48->LC2_F49|";
    OV2C33P65 : LORAX = "1:V14C33,HHR70R5,PA17R5C47->LC1_F48|";
    OV2C32P67 : LORAX = "1:V14C32,HHR80R5,PA21R5C47->LC4_F48|";
    OV3C32P68 : LORAX = "1:V18C32,HHR89R5,PA12R5C45->LC1_F46|";
    OV2C31P69 : LORAX = "1:V14C31,HHR58R5|2:PA15R5C45->LC1_F46|,2:PA15R5C47->LC3_F48,->LC2_F48|,2:PA15R5C48->LC2_F49||";
    OV2C30P70 : LORAX = "1:V14C30,HHR82R5|2:PA19R5C45->LC1_F46|,2:PA19R5C47->LC4_F48,->LC1_F48|,2:PA19R5C48->LC2_F49||";
    LC1_F46 : LORAX = "1:MSW0R5C45|2:V2C45->OV0C45P200|,2:G89R5,PA20R5C47->LC3_F48||";
    LC4_F48 : LORAX = "1:MSW0R5C46|2:V2C46->OV0C46P202|,2:G91R5,PA7R5C45->LC1_F46||";
    LC1_F48 : LORAX = "1:MSW0R5C47|2:V2C47->OV0C47P203|,2:G78R5,PA6R5C48->LC2_F49||";
    LC2_F49 : LORAX = "1:MSW1R5C49|2:V4C49->OV1C49P205|,2:G5R5,PA5R5C47->LC2_F48||";
	LC1_F46 : LORAX2 = "OV3C32P68, OV2C30P70, OV2C31P69, LC4_F48";
	LC4_F48 : LORAX2 = "X, OV2C32P67, OV2C30P70, LC3_F48";
	LC1_F48 : LORAX2 = "X, OV2C33P65, OV2C30P70, LC2_F48";
	LC2_F49 : LORAX2 = "OV3C34P64, OV2C30P70, OV2C31P69, LC1_F48";
	LC3_F48 : LORAX2 = "X, OV2C31P69, LC1_F46, LC1_F48";
	LC2_F48 : LORAX2 = "X, OV2C31P69, LC2_F49, LC4_F48";
END;