de2_ltm_ephoto.map.rpt

友晶科技提供的电子相册源代码

+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                          ; DE2_LTM_Ephoto     ; DE2_LTM_Ephoto     ;
; Family name                                                                    ; Cyclone II         ; Stratix            ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone II/Cyclone III                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Use smart compilation                                                          ; Off                ; Off                ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                               ;
+-------------------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------------+
; File Name with User-Entered Path          ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                            ;
+-------------------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------------+
; Sdram_Control_4Port/command.v             ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/Sdram_Control_4Port/command.v             ;
; Sdram_Control_4Port/control_interface.v   ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/Sdram_Control_4Port/control_interface.v   ;
; Sdram_Control_4Port/sdr_data_path.v       ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/Sdram_Control_4Port/sdr_data_path.v       ;
; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/Sdram_Control_4Port/Sdram_Control_4Port.v ;
; Sdram_Control_4Port/Sdram_PLL.v           ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/Sdram_Control_4Port/Sdram_PLL.v           ;
; Sdram_Control_4Port/Sdram_RD_FIFO.v       ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/Sdram_Control_4Port/Sdram_RD_FIFO.v       ;
; Sdram_Control_4Port/Sdram_WR_FIFO.v       ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/Sdram_Control_4Port/Sdram_WR_FIFO.v       ;
; lcd_timing_controller.v                   ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/lcd_timing_controller.v                   ;
; touch_point_detector.v                    ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/touch_point_detector.v                    ;
; adc_spi_controller.v                      ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/adc_spi_controller.v                      ;
; lcd_spi_cotroller.v                       ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/lcd_spi_cotroller.v                       ;
; three_wire_controller.v                   ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/three_wire_controller.v                   ;
; flash_to_sdram_controller.v               ; yes             ; User Verilog HDL File        ; D:/code/complete/ltm/v1.1/v1.1/DE2_LTM_Ephoto/flash_to_sdram_controller.v               ;