📄 de2_ltm_ephoto.map.rpt
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72. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1|lpm_counter:post_trigger_counter
73. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter
74. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter
75. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_91j2:auto_generated
76. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_91j2:auto_generated|altsyncram_k7l1:altsyncram1
77. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter
78. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter
79. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr
80. Source assignments for sld_hub:sld_hub_inst
81. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
82. Parameter Settings for User Entity Instance: lcd_spi_cotroller:u1
83. Parameter Settings for User Entity Instance: lcd_spi_cotroller:u1|three_wire_controller:u0
84. Parameter Settings for User Entity Instance: adc_spi_controller:u2
85. Parameter Settings for User Entity Instance: touch_point_detector:u3
86. Parameter Settings for User Entity Instance: flash_to_sdram_controller:u4
87. Parameter Settings for User Entity Instance: lcd_timing_controller:u6
88. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7
89. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component
90. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|control_interface:control1
91. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|command:command1
92. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|sdr_data_path:data_path1
93. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component
94. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component
95. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component
96. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component
97. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
98. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
99. Parameter Settings for Inferred Entity Instance: flash_to_sdram_controller:u4|lpm_mult:Mult1
100. Parameter Settings for Inferred Entity Instance: flash_to_sdram_controller:u4|lpm_mult:Mult0
101. dcfifo Parameter Settings by Entity Instance
102. lpm_mult Parameter Settings by Entity Instance
103. SignalTap II Logic Analyzer Settings
104. Analysis & Synthesis INI Usage
105. Analysis & Synthesis Messages
106. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 13 12:03:08 2007 ;
; Quartus II Version ; 7.1 Build 178 06/25/2007 SP 1 SJ Full Version ;
; Revision Name ; DE2_LTM_Ephoto ;
; Top-level Entity Name ; DE2_LTM_Ephoto ;
; Family ; Cyclone II ;
; Total logic elements ; 2,136 ;
; Total combinational functions ; 1,763 ;
; Dedicated logic registers ; 2,136 ;
; Total registers ; 2136 ;
; Total pins ; 429 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 160,768 ;
; Embedded Multiplier 9-bit elements ; 6 ;
; Total PLLs ; 1 ;
+------------------------------------+-----------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
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