de2_ltm_ephoto.map.rpt

友晶科技提供的电子相册源代码

Analysis & Synthesis report for DE2_LTM_Ephoto
Thu Sep 13 12:03:08 2007
Quartus II Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Analysis & Synthesis DSP Block Usage Summary
  9. State Machine - |DE2_LTM_Ephoto|lcd_spi_cotroller:u1|msetup_st
 10. Registers Removed During Synthesis
 11. Removed Registers Triggering Further Register Optimizations
 12. General Register Statistics
 13. Inverted Register Statistics
 14. Multiplexer Restructuring Statistics (Restructuring Performed)
 15. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component
 16. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
 17. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p
 18. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_egc:wrptr_gp
 19. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram
 20. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3
 21. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_brp
 22. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_bwp
 23. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp
 24. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe6
 25. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_brp
 26. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_bwp
 27. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp
 28. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe9
 29. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component
 30. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
 31. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p
 32. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_egc:wrptr_gp
 33. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram
 34. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3
 35. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_brp
 36. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_bwp
 37. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp
 38. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe6
 39. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_brp
 40. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_bwp
 41. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp
 42. Source assignments for Sdram_Control_4Port:u7|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe9
 43. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component
 44. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
 45. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p
 46. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_egc:wrptr_gp
 47. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram
 48. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3
 49. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_brp
 50. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_bwp
 51. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp
 52. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe6
 53. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_brp
 54. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_bwp
 55. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp
 56. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe9
 57. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component
 58. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated
 59. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_fgc:wrptr_g1p
 60. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_egc:wrptr_gp
 61. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram
 62. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|altsyncram_3731:fifo_ram|altsyncram_drg1:altsyncram3
 63. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_brp
 64. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:rs_bwp
 65. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp
 66. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe6
 67. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_brp
 68. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|dffpipe_oe9:ws_bwp
 69. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp
 70. Source assignments for Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe9
 71. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body