de2_ltm_ephoto.jdi

友晶科技提供的电子相册源代码

<sld_project_info>
  <hub_info ir_width="8" node_count="1"/>
  <node_info>
    <node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x28006E00" version="5">
      <parameters>
        <parameter name="lpm_type" type="string" value="sld_signaltap"/>
        <parameter name="sld_node_info" type="unknown" value="671116800"/>
        <parameter name="sld_ip_version" type="dec" value="5"/>
        <parameter name="sld_ip_minor_version" type="dec" value="0"/>
        <parameter name="sld_common_ip_version" type="dec" value="0"/>
        <parameter name="sld_data_bits" type="unknown" value="129"/>
        <parameter name="sld_trigger_bits" type="unknown" value="129"/>
        <parameter name="sld_data_bit_cntr_bits" type="unknown" value="8"/>
        <parameter name="sld_node_crc_bits" type="dec" value="32"/>
        <parameter name="sld_node_crc_hiword" type="unknown" value="4980"/>
        <parameter name="sld_node_crc_loword" type="unknown" value="53915"/>
        <parameter name="sld_incremental_routing" type="dec" value="0"/>
        <parameter name="sld_sample_depth" type="unknown" value="1024"/>
        <parameter name="sld_mem_address_bits" type="unknown" value="10"/>
        <parameter name="sld_ram_block_type" type="string" value="AUTO"/>
        <parameter name="sld_trigger_level" type="unknown" value="1"/>
        <parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
        <parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
        <parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
        <parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
        <parameter name="sld_advanced_trigger_1" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_2" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_3" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_4" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_5" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_6" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_7" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_8" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_9" type="string" value="NONE"/>
        <parameter name="sld_advanced_trigger_10" type="string" value="NONE"/>
        <parameter name="sld_inversion_mask_length" type="unknown" value="406"/>
        <parameter name="sld_inversion_mask" type="unknown" value="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <parameter name="sld_power_up_trigger" type="unknown" value="0"/>
      </parameters>
      <inputs>
        <port name="acq_trigger_in[0]" source="flash_to_sdram_controller:u4|FL_DQ[0]"/>
        <port name="acq_data_in[0]" source="flash_to_sdram_controller:u4|FL_DQ[0]"/>
        <port name="acq_trigger_in[1]" source="flash_to_sdram_controller:u4|FL_DQ[1]"/>
        <port name="acq_data_in[1]" source="flash_to_sdram_controller:u4|FL_DQ[1]"/>
        <port name="acq_trigger_in[2]" source="flash_to_sdram_controller:u4|FL_DQ[2]"/>
        <port name="acq_data_in[2]" source="flash_to_sdram_controller:u4|FL_DQ[2]"/>
        <port name="acq_trigger_in[3]" source="flash_to_sdram_controller:u4|FL_DQ[3]"/>
        <port name="acq_data_in[3]" source="flash_to_sdram_controller:u4|FL_DQ[3]"/>
        <port name="acq_trigger_in[4]" source="flash_to_sdram_controller:u4|FL_DQ[4]"/>
        <port name="acq_data_in[4]" source="flash_to_sdram_controller:u4|FL_DQ[4]"/>
        <port name="acq_trigger_in[5]" source="flash_to_sdram_controller:u4|FL_DQ[5]"/>
        <port name="acq_data_in[5]" source="flash_to_sdram_controller:u4|FL_DQ[5]"/>
        <port name="acq_trigger_in[6]" source="flash_to_sdram_controller:u4|FL_DQ[6]"/>
        <port name="acq_data_in[6]" source="flash_to_sdram_controller:u4|FL_DQ[6]"/>
        <port name="acq_trigger_in[7]" source="flash_to_sdram_controller:u4|FL_DQ[7]"/>
        <port name="acq_data_in[7]" source="flash_to_sdram_controller:u4|FL_DQ[7]"/>
        <port name="acq_trigger_in[8]" source="flash_to_sdram_controller:u4|fl_dq_delay1[0]"/>
        <port name="acq_data_in[8]" source="flash_to_sdram_controller:u4|fl_dq_delay1[0]"/>
        <port name="acq_trigger_in[9]" source="flash_to_sdram_controller:u4|fl_dq_delay1[1]"/>
        <port name="acq_data_in[9]" source="flash_to_sdram_controller:u4|fl_dq_delay1[1]"/>
        <port name="acq_trigger_in[10]" source="flash_to_sdram_controller:u4|fl_dq_delay1[2]"/>
        <port name="acq_data_in[10]" source="flash_to_sdram_controller:u4|fl_dq_delay1[2]"/>
        <port name="acq_trigger_in[11]" source="flash_to_sdram_controller:u4|fl_dq_delay1[3]"/>
        <port name="acq_data_in[11]" source="flash_to_sdram_controller:u4|fl_dq_delay1[3]"/>
        <port name="acq_trigger_in[12]" source="flash_to_sdram_controller:u4|fl_dq_delay1[4]"/>
        <port name="acq_data_in[12]" source="flash_to_sdram_controller:u4|fl_dq_delay1[4]"/>
        <port name="acq_trigger_in[13]" source="flash_to_sdram_controller:u4|fl_dq_delay1[5]"/>
        <port name="acq_data_in[13]" source="flash_to_sdram_controller:u4|fl_dq_delay1[5]"/>
        <port name="acq_trigger_in[14]" source="flash_to_sdram_controller:u4|fl_dq_delay1[6]"/>
        <port name="acq_data_in[14]" source="flash_to_sdram_controller:u4|fl_dq_delay1[6]"/>
        <port name="acq_trigger_in[15]" source="flash_to_sdram_controller:u4|fl_dq_delay1[7]"/>
        <port name="acq_data_in[15]" source="flash_to_sdram_controller:u4|fl_dq_delay1[7]"/>
        <port name="acq_trigger_in[16]" source="flash_to_sdram_controller:u4|fl_dq_delay2[0]"/>
        <port name="acq_data_in[16]" source="flash_to_sdram_controller:u4|fl_dq_delay2[0]"/>
        <port name="acq_trigger_in[17]" source="flash_to_sdram_controller:u4|fl_dq_delay2[1]"/>
        <port name="acq_data_in[17]" source="flash_to_sdram_controller:u4|fl_dq_delay2[1]"/>
        <port name="acq_trigger_in[18]" source="flash_to_sdram_controller:u4|fl_dq_delay2[2]"/>
        <port name="acq_data_in[18]" source="flash_to_sdram_controller:u4|fl_dq_delay2[2]"/>
        <port name="acq_trigger_in[19]" source="flash_to_sdram_controller:u4|fl_dq_delay2[3]"/>
        <port name="acq_data_in[19]" source="flash_to_sdram_controller:u4|fl_dq_delay2[3]"/>
        <port name="acq_trigger_in[20]" source="flash_to_sdram_controller:u4|fl_dq_delay2[4]"/>
        <port name="acq_data_in[20]" source="flash_to_sdram_controller:u4|fl_dq_delay2[4]"/>
        <port name="acq_trigger_in[21]" source="flash_to_sdram_controller:u4|fl_dq_delay2[5]"/>
        <port name="acq_data_in[21]" source="flash_to_sdram_controller:u4|fl_dq_delay2[5]"/>
        <port name="acq_trigger_in[22]" source="flash_to_sdram_controller:u4|fl_dq_delay2[6]"/>
        <port name="acq_data_in[22]" source="flash_to_sdram_controller:u4|fl_dq_delay2[6]"/>
        <port name="acq_trigger_in[23]" source="flash_to_sdram_controller:u4|fl_dq_delay2[7]"/>
        <port name="acq_data_in[23]" source="flash_to_sdram_controller:u4|fl_dq_delay2[7]"/>
        <port name="acq_trigger_in[24]" source="flash_to_sdram_controller:u4|fl_dq_delay3[0]"/>
        <port name="acq_data_in[24]" source="flash_to_sdram_controller:u4|fl_dq_delay3[0]"/>
        <port name="acq_trigger_in[25]" source="flash_to_sdram_controller:u4|fl_dq_delay3[1]"/>
        <port name="acq_data_in[25]" source="flash_to_sdram_controller:u4|fl_dq_delay3[1]"/>
        <port name="acq_trigger_in[26]" source="flash_to_sdram_controller:u4|fl_dq_delay3[2]"/>
        <port name="acq_data_in[26]" source="flash_to_sdram_controller:u4|fl_dq_delay3[2]"/>
        <port name="acq_trigger_in[27]" source="flash_to_sdram_controller:u4|fl_dq_delay3[3]"/>
        <port name="acq_data_in[27]" source="flash_to_sdram_controller:u4|fl_dq_delay3[3]"/>
        <port name="acq_trigger_in[28]" source="flash_to_sdram_controller:u4|fl_dq_delay3[4]"/>
        <port name="acq_data_in[28]" source="flash_to_sdram_controller:u4|fl_dq_delay3[4]"/>
        <port name="acq_trigger_in[29]" source="flash_to_sdram_controller:u4|fl_dq_delay3[5]"/>
        <port name="acq_data_in[29]" source="flash_to_sdram_controller:u4|fl_dq_delay3[5]"/>
        <port name="acq_trigger_in[30]" source="flash_to_sdram_controller:u4|fl_dq_delay3[6]"/>
        <port name="acq_data_in[30]" source="flash_to_sdram_controller:u4|fl_dq_delay3[6]"/>
        <port name="acq_trigger_in[31]" source="flash_to_sdram_controller:u4|fl_dq_delay3[7]"/>
        <port name="acq_data_in[31]" source="flash_to_sdram_controller:u4|fl_dq_delay3[7]"/>
        <port name="acq_trigger_in[32]" source="flash_to_sdram_controller:u4|flash_addr_cnt[0]"/>
        <port name="acq_data_in[32]" source="flash_to_sdram_controller:u4|flash_addr_cnt[0]"/>
        <port name="acq_trigger_in[33]" source="flash_to_sdram_controller:u4|flash_addr_cnt[1]"/>
        <port name="acq_data_in[33]" source="flash_to_sdram_controller:u4|flash_addr_cnt[1]"/>
        <port name="acq_trigger_in[34]" source="flash_to_sdram_controller:u4|flash_addr_o[0]"/>
        <port name="acq_data_in[34]" source="flash_to_sdram_controller:u4|flash_addr_o[0]"/>
        <port name="acq_trigger_in[35]" source="flash_to_sdram_controller:u4|flash_addr_o[10]"/>
        <port name="acq_data_in[35]" source="flash_to_sdram_controller:u4|flash_addr_o[10]"/>
        <port name="acq_trigger_in[36]" source="flash_to_sdram_controller:u4|flash_addr_o[11]"/>
        <port name="acq_data_in[36]" source="flash_to_sdram_controller:u4|flash_addr_o[11]"/>
        <port name="acq_trigger_in[37]" source="flash_to_sdram_controller:u4|flash_addr_o[12]"/>
        <port name="acq_data_in[37]" source="flash_to_sdram_controller:u4|flash_addr_o[12]"/>
        <port name="acq_trigger_in[38]" source="flash_to_sdram_controller:u4|flash_addr_o[13]"/>
        <port name="acq_data_in[38]" source="flash_to_sdram_controller:u4|flash_addr_o[13]"/>
        <port name="acq_trigger_in[39]" source="flash_to_sdram_controller:u4|flash_addr_o[14]"/>
        <port name="acq_data_in[39]" source="flash_to_sdram_controller:u4|flash_addr_o[14]"/>
        <port name="acq_trigger_in[40]" source="flash_to_sdram_controller:u4|flash_addr_o[15]"/>
        <port name="acq_data_in[40]" source="flash_to_sdram_controller:u4|flash_addr_o[15]"/>
        <port name="acq_trigger_in[41]" source="flash_to_sdram_controller:u4|flash_addr_o[16]"/>
        <port name="acq_data_in[41]" source="flash_to_sdram_controller:u4|flash_addr_o[16]"/>
        <port name="acq_trigger_in[42]" source="flash_to_sdram_controller:u4|flash_addr_o[17]"/>
        <port name="acq_data_in[42]" source="flash_to_sdram_controller:u4|flash_addr_o[17]"/>
        <port name="acq_trigger_in[43]" source="flash_to_sdram_controller:u4|flash_addr_o[18]"/>
        <port name="acq_data_in[43]" source="flash_to_sdram_controller:u4|flash_addr_o[18]"/>
        <port name="acq_trigger_in[44]" source="flash_to_sdram_controller:u4|flash_addr_o[19]"/>
        <port name="acq_data_in[44]" source="flash_to_sdram_controller:u4|flash_addr_o[19]"/>
        <port name="acq_trigger_in[45]" source="flash_to_sdram_controller:u4|flash_addr_o[1]"/>
        <port name="acq_data_in[45]" source="flash_to_sdram_controller:u4|flash_addr_o[1]"/>
        <port name="acq_trigger_in[46]" source="flash_to_sdram_controller:u4|flash_addr_o[20]"/>
        <port name="acq_data_in[46]" source="flash_to_sdram_controller:u4|flash_addr_o[20]"/>
        <port name="acq_trigger_in[47]" source="flash_to_sdram_controller:u4|flash_addr_o[21]"/>
        <port name="acq_data_in[47]" source="flash_to_sdram_controller:u4|flash_addr_o[21]"/>
        <port name="acq_trigger_in[48]" source="flash_to_sdram_controller:u4|flash_addr_o[22]"/>
        <port name="acq_data_in[48]" source="flash_to_sdram_controller:u4|flash_addr_o[22]"/>
        <port name="acq_trigger_in[49]" source="flash_to_sdram_controller:u4|flash_addr_o[2]"/>
        <port name="acq_data_in[49]" source="flash_to_sdram_controller:u4|flash_addr_o[2]"/>
        <port name="acq_trigger_in[50]" source="flash_to_sdram_controller:u4|flash_addr_o[3]"/>
        <port name="acq_data_in[50]" source="flash_to_sdram_controller:u4|flash_addr_o[3]"/>
        <port name="acq_trigger_in[51]" source="flash_to_sdram_controller:u4|flash_addr_o[4]"/>
        <port name="acq_data_in[51]" source="flash_to_sdram_controller:u4|flash_addr_o[4]"/>
        <port name="acq_trigger_in[52]" source="flash_to_sdram_controller:u4|flash_addr_o[5]"/>
        <port name="acq_data_in[52]" source="flash_to_sdram_controller:u4|flash_addr_o[5]"/>
        <port name="acq_trigger_in[53]" source="flash_to_sdram_controller:u4|flash_addr_o[6]"/>
        <port name="acq_data_in[53]" source="flash_to_sdram_controller:u4|flash_addr_o[6]"/>
        <port name="acq_trigger_in[54]" source="flash_to_sdram_controller:u4|flash_addr_o[7]"/>
        <port name="acq_data_in[54]" source="flash_to_sdram_controller:u4|flash_addr_o[7]"/>
        <port name="acq_trigger_in[55]" source="flash_to_sdram_controller:u4|flash_addr_o[8]"/>
        <port name="acq_data_in[55]" source="flash_to_sdram_controller:u4|flash_addr_o[8]"/>
        <port name="acq_trigger_in[56]" source="flash_to_sdram_controller:u4|flash_addr_o[9]"/>