📄 de2_ltm_ephoto.v
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output ENET_WR_N; // DM9000A Write
output ENET_RD_N; // DM9000A Read
output ENET_RST_N; // DM9000A Reset
input ENET_INT; // DM9000A Interrupt
output ENET_CLK; // DM9000A Clock 25 MHz
//////////////////// Audio CODEC ////////////////////////////
inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////// TV Devoder ////////////////////////////
input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
input TD_HS; // TV Decoder H_SYNC
input TD_VS; // TV Decoder V_SYNC
output TD_RESET; // TV Decoder Reset
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
////////////////////////////
// All inout port turn to tri-state
assign DRAM_DQ = 16'hzzzz;
assign OTG_DATA = 16'hzzzz;
assign LCD_DATA = 8'hzz;
assign SD_DAT = 1'bz;
assign ENET_DATA = 16'hzzzz;
assign AUD_ADCLRCK = 1'bz;
assign AUD_DACLRCK = 1'bz;
assign AUD_BCLK = 1'bz;
assign GPIO_1 = 36'hzzzzzzzzz;
//=============================================================================
// REG/WIRE declarations
//=============================================================================
// Touch panel signal //
wire [7:0] ltm_r; // LTM Red Data 8 Bits
wire [7:0] ltm_g; // LTM Green Data 8 Bits
wire [7:0] ltm_b; // LTM Blue Data 8 Bits
wire ltm_nclk; // LTM Clcok
wire ltm_hd;
wire ltm_vd;
wire ltm_den;
wire adc_dclk;
wire adc_cs;
wire adc_penirq_n;
wire adc_busy;
wire adc_din;
wire adc_dout;
wire adc_ltm_sclk;
wire ltm_grst;
// LTM Config//
wire ltm_sclk;
wire ltm_sda;
wire ltm_scen;
wire ltm_3wirebusy_n;
wire [11:0] x_coord;
wire [11:0] y_coord;
wire new_coord;
wire [2:0] photo_cnt;
// clock
wire F_CLK;// flash read clock
reg [31:0] div;
// sdram to touch panel timing
wire mRead;
wire [15:0] Read_DATA1;
wire [15:0] Read_DATA2;
// flash to sdram sdram
wire [7:0] sRED;// flash to sdram red pixel data
wire [7:0] sGREEN;// flash to sdram green pixel data
wire [7:0] sBLUE;// flash to sdram blue pixel data
wire sdram_write_en; // flash to sdram write control
wire sdram_write; // sdram write signal
// system reset
wire DLY0;
wire DLY1;
wire DLY2;
//=============================================================================
// Structural coding
//=============================================================================
//////////////////////////////////////////
assign adc_penirq_n =GPIO_0[0];
assign adc_dout =GPIO_0[1];
assign adc_busy =GPIO_0[2];
assign GPIO_0[3] =adc_din;
assign GPIO_0[4] =adc_ltm_sclk;
assign GPIO_0[5] =ltm_b[3];
assign GPIO_0[6] =ltm_b[2];
assign GPIO_0[7] =ltm_b[1];
assign GPIO_0[8] =ltm_b[0];
assign GPIO_0[9] =ltm_nclk;
assign GPIO_0[10] =ltm_den;
assign GPIO_0[11] =ltm_hd;
assign GPIO_0[12] =ltm_vd;
assign GPIO_0[13] =ltm_b[4];
assign GPIO_0[14] =ltm_b[5];
assign GPIO_0[15] =ltm_b[6];
assign GPIO_0[16] =ltm_b[7];
assign GPIO_0[17] =ltm_g[0];
assign GPIO_0[18] =ltm_g[1];
assign GPIO_0[19] =ltm_g[2];
assign GPIO_0[20] =ltm_g[3];
assign GPIO_0[21] =ltm_g[4];
assign GPIO_0[22] =ltm_g[5];
assign GPIO_0[23] =ltm_g[6];
assign GPIO_0[24] =ltm_g[7];
assign GPIO_0[25] =ltm_r[0];
assign GPIO_0[26] =ltm_r[1];
assign GPIO_0[27] =ltm_r[2];
assign GPIO_0[28] =ltm_r[3];
assign GPIO_0[29] =ltm_r[4];
assign GPIO_0[30] =ltm_r[5];
assign GPIO_0[31] =ltm_r[6];
assign GPIO_0[32] =ltm_r[7];
assign GPIO_0[33] =ltm_grst;
assign GPIO_0[34] =ltm_scen;
assign GPIO_0[35] =ltm_sda;
////////////////////////////////////////
assign ltm_grst = KEY[0];
assign F_CLK = div[3];
assign adc_ltm_sclk = ( adc_dclk & ltm_3wirebusy_n ) | ( ~ltm_3wirebusy_n & ltm_sclk );
always @( posedge CLOCK_50 )
begin
div <= div+1;
end
///////////////////////////////////////////////////////////////
lcd_spi_cotroller u1 (
// Host Side
.iCLK(CLOCK_50),
.iRST_n(DLY0),
// 3 wire Side
.o3WIRE_SCLK(ltm_sclk),
.io3WIRE_SDAT(ltm_sda),
.o3WIRE_SCEN(ltm_scen),
.o3WIRE_BUSY_n(ltm_3wirebusy_n)
);
adc_spi_controller u2 (
.iCLK(CLOCK_50),
.iRST_n(DLY0),
.oADC_DIN(adc_din),
.oADC_DCLK(adc_dclk),
.oADC_CS(adc_cs),
.iADC_DOUT(adc_dout),
.iADC_BUSY(adc_busy),
.iADC_PENIRQ_n(adc_penirq_n),
.oX_COORD(x_coord),
.oY_COORD(y_coord),
.oNEW_COORD(new_coord),
);
touch_point_detector u3 (
.iCLK(CLOCK_50),
.iRST_n(DLY0),
.iX_COORD(x_coord),
.iY_COORD(y_coord),
.iNEW_COORD(new_coord),
.iSDRAM_WRITE_EN(sdram_write_en),
.oPHOTO_CNT(photo_cnt),
);
flash_to_sdram_controller u4 (
.iPHOTO_NUM(photo_cnt),
.iRST_n(DLY1) ,
.iF_CLK(F_CLK),
.FL_DQ(FL_DQ) ,
.oFL_ADDR(FL_ADDR) ,
.oFL_WE_N(FL_WE_N) ,
.oFL_RST_n(FL_RST_N),
.oFL_OE_N(FL_OE_N) ,
.oFL_CE_N(FL_CE_N) ,
.oSDRAM_WRITE_EN(sdram_write_en),
.oSDRAM_WRITE(sdram_write),
.oRED(sRED),
.oGREEN(sGREEN),
.oBLUE(sBLUE),
);
SEG7_LUT_8 u5 (
.oSEG0(HEX0),
.oSEG1(HEX1),
.oSEG2(HEX2),
.oSEG3(HEX3),
.oSEG4(HEX4),
.oSEG5(HEX5),
.oSEG6(HEX6),
.oSEG7(HEX7),
.iDIG({4'h0,x_coord,4'h0,y_coord}),
.ON_OFF(8'b01110111)
);
lcd_timing_controller u6 (
.iCLK(ltm_nclk),
.iRST_n(DLY2),
// sdram side
.iREAD_DATA1(Read_DATA1),
.iREAD_DATA2(Read_DATA2),
.oREAD_SDRAM_EN(mRead),
// lcd side
.oLCD_R(ltm_r),
.oLCD_G(ltm_g),
.oLCD_B(ltm_b),
.oHD(ltm_hd),
.oVD(ltm_vd),
.oDEN(ltm_den)
);
// SDRAM frame buffer
Sdram_Control_4Port u7 ( // HOST Side
.REF_CLK(CLOCK_50),
.RESET_N(1'b1),
// FIFO Write Side 1
.WR1_DATA({sRED,sGREEN}),
.WR1(sdram_write),
.WR1_FULL(WR1_FULL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(800*480),
.WR1_LENGTH(9'h80),
.WR1_LOAD(!DLY0),
.WR1_CLK(F_CLK),
// FIFO Write Side 2
.WR2_DATA({8'h0,sBLUE}),
.WR2(sdram_write),
.WR2_ADDR(22'h100000),
.WR2_MAX_ADDR(22'h100000+800*480),
.WR2_LENGTH(9'h80),
.WR2_LOAD(!DLY0),
.WR2_CLK(F_CLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(mRead),
.RD1_ADDR(0),
.RD1_MAX_ADDR(800*480),
.RD1_LENGTH(9'h80),
.RD1_LOAD(!DLY0),
.RD1_CLK(ltm_nclk),
// FIFO Read Side 2
.RD2_DATA(Read_DATA2),
.RD2(mRead),
.RD2_ADDR(22'h100000),
.RD2_MAX_ADDR(22'h100000+800*480),
.RD2_LENGTH(9'h80),
.RD2_LOAD(!DLY0),
.RD2_CLK(ltm_nclk),
// SDRAM Side
.SA(DRAM_ADDR),
.BA({DRAM_BA_1,DRAM_BA_0}),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK),
.CLK_33(ltm_nclk)
);
Reset_Delay u8 (.iCLK(CLOCK_50),
.iRST(KEY[0]),
.oRST_0(DLY0),
.oRST_1(DLY1),
.oRST_2(DLY2)
);
endmodule⌨️ 快捷键说明
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