de2_ltm_ephoto.tan.summary

友晶科技提供的电子相册源代码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.477 ns
From           : DRAM_DQ[7]
To             : Sdram_Control_4Port:u7|mDATAOUT[7]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.031 ns
From           : adc_spi_controller:u2|oY_COORD[8]
To             : HEX2[2]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 8.340 ns
From           : KEY[0]
To             : GPIO_0[33]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.432 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack          : -2.186 ns
Required Time  : 120.00 MHz ( period = 8.333 ns )
Actual Time    : N/A
From           : Reset_Delay:u8|oRST_0
To             : Sdram_Control_4Port:u7|WR_MASK[0]
From Clock     : CLOCK_50
To Clock       : Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths   : 86

Type           : Clock Setup: 'CLOCK_50'
Slack          : 6.731 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 152.95 MHz ( period = 6.538 ns )
From           : lcd_spi_cotroller:u1|m3wire_data[14]
To             : lcd_spi_cotroller:u1|three_wire_controller:u0|mSDATA
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2'
Slack          : 22.273 ns
Required Time  : 33.33 MHz ( period = 30.000 ns )
Actual Time    : 129.42 MHz ( period = 7.727 ns )
From           : lcd_timing_controller:u6|y_cnt[2]
To             : Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]
From Clock     : Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2
To Clock       : Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 131.51 MHz ( period = 7.604 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5]
To             : sld_hub:sld_hub_inst|hub_tdo_reg
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_50'
Slack          : -2.579 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : touch_point_detector:u3|photo_cnt[1]~_Duplicate_2
To             : flash_to_sdram_controller:u4|d1_photo_num[1]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 15

Type           : Clock Hold: 'Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack          : 0.391 ns
Required Time  : 120.00 MHz ( period = 8.333 ns )
Actual Time    : N/A
From           : Sdram_Control_4Port:u7|command:command1|rw_flag
To             : Sdram_Control_4Port:u7|command:command1|rw_flag
From Clock     : Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
To Clock       : Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2'
Slack          : 0.513 ns
Required Time  : 33.33 MHz ( period = 30.000 ns )
Actual Time    : N/A
From           : Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe6|dffe7a[8]
To             : Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe6|dffe8a[8]
From Clock     : Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2
To Clock       : Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 101

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