seg70.fit.summary

CPLD开发板VHDL源程序并附上开发板的原理图

Fitter Status : Successful - Sat Oct 11 21:19:29 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : seg70
Top-level Entity Name : seg70
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Total logic elements : 30 / 240 ( 13 % )
Total pins : 18 / 80 ( 23 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )