seg70.tan.rpt

CPLD开发板VHDL源程序并附上开发板的原理图

+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+--------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To         ; From Clock ;
+-------+--------------+------------+--------------+------------+------------+
; N/A   ; None         ; 10.342 ns  ; cnt_scan[15] ; en[2]      ; clk        ;
; N/A   ; None         ; 10.197 ns  ; cnt_scan[14] ; en[2]      ; clk        ;
; N/A   ; None         ; 10.189 ns  ; cnt_scan[15] ; dataout[7] ; clk        ;
; N/A   ; None         ; 10.151 ns  ; cnt_scan[15] ; dataout[2] ; clk        ;
; N/A   ; None         ; 10.138 ns  ; cnt_scan[15] ; en[1]      ; clk        ;
; N/A   ; None         ; 10.053 ns  ; cnt_scan[15] ; en[3]      ; clk        ;
; N/A   ; None         ; 10.046 ns  ; cnt_scan[14] ; dataout[7] ; clk        ;
; N/A   ; None         ; 10.008 ns  ; cnt_scan[14] ; dataout[2] ; clk        ;
; N/A   ; None         ; 10.006 ns  ; cnt_scan[15] ; en[4]      ; clk        ;
; N/A   ; None         ; 9.994 ns   ; cnt_scan[14] ; en[1]      ; clk        ;
; N/A   ; None         ; 9.982 ns   ; cnt_scan[15] ; dataout[6] ; clk        ;
; N/A   ; None         ; 9.981 ns   ; cnt_scan[13] ; en[2]      ; clk        ;
; N/A   ; None         ; 9.904 ns   ; cnt_scan[14] ; en[3]      ; clk        ;
; N/A   ; None         ; 9.857 ns   ; cnt_scan[14] ; en[4]      ; clk        ;
; N/A   ; None         ; 9.709 ns   ; cnt_scan[13] ; dataout[7] ; clk        ;
; N/A   ; None         ; 9.684 ns   ; cnt_scan[15] ; en[7]      ; clk        ;
; N/A   ; None         ; 9.671 ns   ; cnt_scan[13] ; dataout[2] ; clk        ;
; N/A   ; None         ; 9.660 ns   ; cnt_scan[14] ; dataout[6] ; clk        ;
; N/A   ; None         ; 9.657 ns   ; cnt_scan[13] ; en[1]      ; clk        ;
; N/A   ; None         ; 9.567 ns   ; cnt_scan[13] ; en[3]      ; clk        ;
; N/A   ; None         ; 9.557 ns   ; cnt_scan[14] ; en[7]      ; clk        ;
; N/A   ; None         ; 9.520 ns   ; cnt_scan[15] ; dataout[1] ; clk        ;
; N/A   ; None         ; 9.517 ns   ; cnt_scan[13] ; en[7]      ; clk        ;
; N/A   ; None         ; 9.514 ns   ; cnt_scan[13] ; en[4]      ; clk        ;
; N/A   ; None         ; 9.394 ns   ; cnt_scan[14] ; dataout[1] ; clk        ;
; N/A   ; None         ; 9.353 ns   ; cnt_scan[13] ; dataout[1] ; clk        ;
; N/A   ; None         ; 9.285 ns   ; cnt_scan[13] ; dataout[6] ; clk        ;
; N/A   ; None         ; 9.271 ns   ; cnt_scan[15] ; dataout[5] ; clk        ;
; N/A   ; None         ; 9.126 ns   ; cnt_scan[14] ; dataout[5] ; clk        ;
; N/A   ; None         ; 8.941 ns   ; cnt_scan[15] ; en[5]      ; clk        ;
; N/A   ; None         ; 8.941 ns   ; cnt_scan[15] ; dataout[3] ; clk        ;
; N/A   ; None         ; 8.933 ns   ; cnt_scan[15] ; en[6]      ; clk        ;
; N/A   ; None         ; 8.932 ns   ; cnt_scan[15] ; en[0]      ; clk        ;
; N/A   ; None         ; 8.910 ns   ; cnt_scan[13] ; dataout[5] ; clk        ;
; N/A   ; None         ; 8.896 ns   ; cnt_scan[15] ; dataout[4] ; clk        ;
; N/A   ; None         ; 8.800 ns   ; cnt_scan[14] ; dataout[3] ; clk        ;
; N/A   ; None         ; 8.799 ns   ; cnt_scan[14] ; en[5]      ; clk        ;
; N/A   ; None         ; 8.792 ns   ; cnt_scan[14] ; en[6]      ; clk        ;
; N/A   ; None         ; 8.790 ns   ; cnt_scan[14] ; en[0]      ; clk        ;
; N/A   ; None         ; 8.574 ns   ; cnt_scan[14] ; dataout[4] ; clk        ;
; N/A   ; None         ; 8.463 ns   ; cnt_scan[13] ; dataout[3] ; clk        ;
; N/A   ; None         ; 8.462 ns   ; cnt_scan[13] ; en[5]      ; clk        ;
; N/A   ; None         ; 8.455 ns   ; cnt_scan[13] ; en[6]      ; clk        ;
; N/A   ; None         ; 8.453 ns   ; cnt_scan[13] ; en[0]      ; clk        ;
; N/A   ; None         ; 8.199 ns   ; cnt_scan[13] ; dataout[4] ; clk        ;
+-------+--------------+------------+--------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Oct 11 21:19:38 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seg70 -c seg70
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 201.09 MHz between source register "cnt_scan[3]" and destination register "cnt_scan[12]" (period= 4.973 ns)
    Info: + Longest register to register delay is 4.264 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y4_N5; Fanout = 3; REG Node = 'cnt_scan[3]'
        Info: 2: + IC(0.892 ns) + CELL(0.978 ns) = 1.870 ns; Loc. = LC_X3_Y4_N5; Fanout = 2; COMB Node = 'cnt_scan[3]~82'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.993 ns; Loc. = LC_X3_Y4_N6; Fanout = 2; COMB Node = 'cnt_scan[4]~81'
        Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.116 ns; Loc. = LC_X3_Y4_N7; Fanout = 2; COMB Node = 'cnt_scan[5]~80'
        Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.239 ns; Loc. = LC_X3_Y4_N8; Fanout = 2; COMB Node = 'cnt_scan[6]~79'
        Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 2.638 ns; Loc. = LC_X3_Y4_N9; Fanout = 6; COMB Node = 'cnt_scan[7]~78'
        Info: 7: + IC(0.000 ns) + CELL(1.626 ns) = 4.264 ns; Loc. = LC_X4_Y4_N4; Fanout = 2; REG Node = 'cnt_scan[12]'
        Info: Total cell delay = 3.372 ns ( 79.08 % )
        Info: Total interconnect delay = 0.892 ns ( 20.92 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y4_N4; Fanout = 2; REG Node = 'cnt_scan[12]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y4_N5; Fanout = 3; REG Node = 'cnt_scan[3]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "en[2]" through register "cnt_scan[15]" is 10.342 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y4_N7; Fanout = 15; REG Node = 'cnt_scan[15]'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 6.618 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N7; Fanout = 15; REG Node = 'cnt_scan[15]'
        Info: 2: + IC(1.825 ns) + CELL(0.740 ns) = 2.565 ns; Loc. = LC_X2_Y4_N2; Fanout = 2; COMB Node = 'Mux7~94'
        Info: 3: + IC(1.731 ns) + CELL(2.322 ns) = 6.618 ns; Loc. = PIN_98; Fanout = 0; PIN Node = 'en[2]'
        Info: Total cell delay = 3.062 ns ( 46.27 % )
        Info: Total interconnect delay = 3.556 ns ( 53.73 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 109 megabytes of memory during processing
    Info: Processing ended: Sat Oct 11 21:19:39 2008
    Info: Elapsed time: 00:00:01