seg70.fit.rpt

CPLD开发板VHDL源程序并附上开发板的原理图

+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                    ;
+--------------------------------------------------------------------------------+---------+
; Name                                                                           ; Value   ;
+--------------------------------------------------------------------------------+---------+
; Mid Wire Use - Fit Attempt 1                                                   ; 5       ;
; Mid Slack - Fit Attempt 1                                                      ; -9124   ;
; Internal Atom Count - Fit Attempt 1                                            ; 30      ;
; LE/ALM Count - Fit Attempt 1                                                   ; 30      ;
; LAB Count - Fit Attempt 1                                                      ; 4       ;
; Outputs per Lab - Fit Attempt 1                                                ; 4.250   ;
; Inputs per LAB - Fit Attempt 1                                                 ; 1.500   ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.000   ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:4     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:4     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:4     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:4     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:2;1:2 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:2;1:2 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:4     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:4     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:4     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:2;2:2 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:2;1:2 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:4     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:2;1:2 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:4     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:2;1:2 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:2;1:2 ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:4     ;
; LEs in Chains - Fit Attempt 1                                                  ; 15      ;
; LEs in Long Chains - Fit Attempt 1                                             ; 15      ;
; LABs with Chains - Fit Attempt 1                                               ; 2       ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0       ;
; Time - Fit Attempt 1                                                           ; 0       ;
+--------------------------------------------------------------------------------+---------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Wire Use - Fit Attempt 1      ; 1     ;
; Early Slack - Fit Attempt 1         ; -9781 ;
; Mid Wire Use - Fit Attempt 1        ; 2     ;
; Mid Slack - Fit Attempt 1           ; -8962 ;
; Late Wire Use - Fit Attempt 1       ; 2     ;
; Late Slack - Fit Attempt 1          ; -9069 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000 ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.093 ;
+-------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -9232 ;
; Early Wire Use - Fit Attempt 1      ; 1     ;
; Peak Regional Wire - Fit Attempt 1  ; 1     ;
; Mid Slack - Fit Attempt 1           ; -9941 ;
; Late Slack - Fit Attempt 1          ; -9941 ;
; Late Slack - Fit Attempt 1          ; -9941 ;
; Late Wire Use - Fit Attempt 1       ; 1     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.031 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Oct 11 21:19:27 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off seg70 -c seg70
Info: Selected device EPM240T100C5 for design "seg70"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Warning: No exact pin location assignment(s) for 18 pins of 18 total pins
    Info: Pin dataout[0] not assigned to an exact location on the device
    Info: Pin dataout[1] not assigned to an exact location on the device
    Info: Pin dataout[2] not assigned to an exact location on the device
    Info: Pin dataout[3] not assigned to an exact location on the device
    Info: Pin dataout[4] not assigned to an exact location on the device
    Info: Pin dataout[5] not assigned to an exact location on the device
    Info: Pin dataout[6] not assigned to an exact location on the device
    Info: Pin dataout[7] not assigned to an exact location on the device
    Info: Pin en[0] not assigned to an exact location on the device
    Info: Pin en[1] not assigned to an exact location on the device
    Info: Pin en[2] not assigned to an exact location on the device
    Info: Pin en[3] not assigned to an exact location on the device
    Info: Pin en[4] not assigned to an exact location on the device
    Info: Pin en[5] not assigned to an exact location on the device
    Info: Pin en[6] not assigned to an exact location on the device
    Info: Pin en[7] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin rst not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 14
Info: Automatically promoted signal "rst" to use Global clock in PIN 12
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 16 (unused VREF, 3.30 VCCIO, 0 input, 16 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  36 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 5.821 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y4; Fanout = 17; REG Node = 'cnt_scan[13]'
    Info: 2: + IC(1.557 ns) + CELL(0.200 ns) = 1.757 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'Mux7~98'
    Info: 3: + IC(1.742 ns) + CELL(2.322 ns) = 5.821 ns; Loc. = PIN_81; Fanout = 0; PIN Node = 'en[4]'
    Info: Total cell delay = 2.522 ns ( 43.33 % )
    Info: Total interconnect delay = 3.299 ns ( 56.67 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin dataout[0] has VCC driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/7段数码管/seg70/seg70.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 170 megabytes of memory during processing
    Info: Processing ended: Sat Oct 11 21:19:30 2008
    Info: Elapsed time: 00:00:03


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/7段数码管/seg70/seg70.fit.smsg.