i2c.tan.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register inner_state\[3\] register sda_buf 29.41 MHz 34.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 29.41 MHz between source register \"inner_state\[3\]\" and destination register \"sda_buf\" (period= 34.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "29.000 ns + Longest register register " "Info: + Longest register to register delay is 29.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inner_state\[3\] 1 REG LC5 166 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 166; REG Node = 'inner_state\[3\]'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "" { inner_state[3] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns Mux~17879 2 COMB LC62 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC62; Fanout = 1; COMB Node = 'Mux~17879'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "8.000 ns" { inner_state[3] Mux~17879 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns Mux~17881 3 COMB LC63 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC63; Fanout = 1; COMB Node = 'Mux~17881'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "1.000 ns" { Mux~17879 Mux~17881 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 11.000 ns Mux~17780 4 COMB LC64 3 " "Info: 4: + IC(0.000 ns) + CELL(2.000 ns) = 11.000 ns; Loc. = LC64; Fanout = 3; COMB Node = 'Mux~17780'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "2.000 ns" { Mux~17881 Mux~17780 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 19.000 ns Mux~17899 5 COMB LC55 1 " "Info: 5: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC55; Fanout = 1; COMB Node = 'Mux~17899'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "8.000 ns" { Mux~17780 Mux~17899 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 21.000 ns Mux~17805 6 COMB LC56 1 " "Info: 6: + IC(0.000 ns) + CELL(2.000 ns) = 21.000 ns; Loc. = LC56; Fanout = 1; COMB Node = 'Mux~17805'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "2.000 ns" { Mux~17899 Mux~17805 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 29.000 ns sda_buf 7 REG LC38 50 " "Info: 7: + IC(2.000 ns) + CELL(6.000 ns) = 29.000 ns; Loc. = LC38; Fanout = 50; REG Node = 'sda_buf'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "8.000 ns" { Mux~17805 sda_buf } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.000 ns 79.31 % " "Info: Total cell delay = 23.000 ns ( 79.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 20.69 % " "Info: Total interconnect delay = 6.000 ns ( 20.69 % )" {  } {  } 0}  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "29.000 ns" { inner_state[3] Mux~17879 Mux~17881 Mux~17780 Mux~17899 Mux~17805 sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "29.000 ns" { inner_state[3] Mux~17879 Mux~17881 Mux~17780 Mux~17899 Mux~17805 sda_buf } { 0.000ns 2.000ns 0.000ns 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 6.000ns 1.000ns 2.000ns 6.000ns 2.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 70 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 70; CLK Node = 'clk'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns sda_buf 2 REG LC38 50 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC38; Fanout = 50; REG Node = 'sda_buf'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "0.000 ns" { clk sda_buf } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "3.000 ns" { clk sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out sda_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 70 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 70; CLK Node = 'clk'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns inner_state\[3\] 2 REG LC5 166 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC5; Fanout = 166; REG Node = 'inner_state\[3\]'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "0.000 ns" { clk inner_state[3] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "3.000 ns" { clk inner_state[3] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out inner_state[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "3.000 ns" { clk sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out sda_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "3.000 ns" { clk inner_state[3] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out inner_state[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 32 -1 0 } }  } 0}  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "29.000 ns" { inner_state[3] Mux~17879 Mux~17881 Mux~17780 Mux~17899 Mux~17805 sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "29.000 ns" { inner_state[3] Mux~17879 Mux~17881 Mux~17780 Mux~17899 Mux~17805 sda_buf } { 0.000ns 2.000ns 0.000ns 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 6.000ns 1.000ns 2.000ns 6.000ns 2.000ns 6.000ns } } } { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "3.000 ns" { clk sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out sda_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "3.000 ns" { clk inner_state[3] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out inner_state[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sda_buf sda clk 30.000 ns register " "Info: tsu for register \"sda_buf\" (data pin = \"sda\", clock pin = \"clk\") is 30.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "29.000 ns + Longest pin register " "Info: + Longest pin to register delay is 29.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 PIN PIN_29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'sda'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "" { sda } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns sda~0 2 COMB IO38 19 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = IO38; Fanout = 19; COMB Node = 'sda~0'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "2.000 ns" { sda sda~0 } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns Mux~17893 3 COMB LC58 1 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC58; Fanout = 1; COMB Node = 'Mux~17893'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "8.000 ns" { sda~0 Mux~17893 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 12.000 ns Mux~17786 4 COMB LC59 3 " "Info: 4: + IC(0.000 ns) + CELL(2.000 ns) = 12.000 ns; Loc. = LC59; Fanout = 3; COMB Node = 'Mux~17786'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "2.000 ns" { Mux~17893 Mux~17786 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 21.000 ns Mux~17805 5 COMB LC56 1 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 21.000 ns; Loc. = LC56; Fanout = 1; COMB Node = 'Mux~17805'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "9.000 ns" { Mux~17786 Mux~17805 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 29.000 ns sda_buf 6 REG LC38 50 " "Info: 6: + IC(2.000 ns) + CELL(6.000 ns) = 29.000 ns; Loc. = LC38; Fanout = 50; REG Node = 'sda_buf'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "8.000 ns" { Mux~17805 sda_buf } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.000 ns 79.31 % " "Info: Total cell delay = 23.000 ns ( 79.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 20.69 % " "Info: Total interconnect delay = 6.000 ns ( 20.69 % )" {  } {  } 0}  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "29.000 ns" { sda sda~0 Mux~17893 Mux~17786 Mux~17805 sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "29.000 ns" { sda sda~0 Mux~17893 Mux~17786 Mux~17805 sda_buf } { 0.000ns 0.000ns 2.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns 2.000ns 7.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 70 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 70; CLK Node = 'clk'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns sda_buf 2 REG LC38 50 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC38; Fanout = 50; REG Node = 'sda_buf'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "0.000 ns" { clk sda_buf } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "3.000 ns" { clk sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out sda_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "29.000 ns" { sda sda~0 Mux~17893 Mux~17786 Mux~17805 sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "29.000 ns" { sda sda~0 Mux~17893 Mux~17786 Mux~17805 sda_buf } { 0.000ns 0.000ns 2.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns 2.000ns 7.000ns 6.000ns } } } { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "3.000 ns" { clk sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out sda_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[1\] en_xhdl3\[0\] 28.000 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[1\]\" through register \"en_xhdl3\[0\]\" is 28.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 70 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 70; CLK Node = 'clk'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns en_xhdl3\[0\] 2 REG LC118 62 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC118; Fanout = 62; REG Node = 'en_xhdl3\[0\]'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "0.000 ns" { clk en_xhdl3[0] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 70 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "3.000 ns" { clk en_xhdl3[0] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out en_xhdl3[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 70 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.000 ns + Longest register pin " "Info: + Longest register to pin delay is 24.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en_xhdl3\[0\] 1 REG LC118 62 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC118; Fanout = 62; REG Node = 'en_xhdl3\[0\]'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "" { en_xhdl3[0] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 70 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns reduce_or~2542 2 COMB LC100 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC100; Fanout = 1; COMB Node = 'reduce_or~2542'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "8.000 ns" { en_xhdl3[0] reduce_or~2542 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns reduce_or~2512 3 COMB LC101 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC101; Fanout = 1; COMB Node = 'reduce_or~2512'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "1.000 ns" { reduce_or~2542 reduce_or~2512 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 11.000 ns reduce_or~2460 4 COMB LC102 1 " "Info: 4: + IC(0.000 ns) + CELL(2.000 ns) = 11.000 ns; Loc. = LC102; Fanout = 1; COMB Node = 'reduce_or~2460'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "2.000 ns" { reduce_or~2512 reduce_or~2460 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 20.000 ns reduce_or~2543 5 COMB LC99 1 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC99; Fanout = 1; COMB Node = 'reduce_or~2543'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "9.000 ns" { reduce_or~2460 reduce_or~2543 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 24.000 ns seg_data\[1\] 6 PIN PIN_64 0 " "Info: 6: + IC(0.000 ns) + CELL(4.000 ns) = 24.000 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'seg_data\[1\]'" {  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "4.000 ns" { reduce_or~2543 seg_data[1] } "NODE_NAME" } "" } } { "i2c.vhd" "" { Text "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/i2c.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "20.000 ns 83.33 % " "Info: Total cell delay = 20.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 16.67 % " "Info: Total interconnect delay = 4.000 ns ( 16.67 % )" {  } {  } 0}  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "24.000 ns" { en_xhdl3[0] reduce_or~2542 reduce_or~2512 reduce_or~2460 reduce_or~2543 seg_data[1] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "24.000 ns" { en_xhdl3[0] reduce_or~2542 reduce_or~2512 reduce_or~2460 reduce_or~2543 seg_data[1] } { 0.000ns 2.000ns 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}  } { { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "3.000 ns" { clk en_xhdl3[0] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out en_xhdl3[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "G:/work_room/PLD/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/i2c总线/" "" "24.000 ns" { en_xhdl3[0] reduce_or~2542 reduce_or~2512 reduce_or~2460 reduce_or~2543 seg_data[1] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "24.000 ns" { en_xhdl3[0] reduce_or~2542 reduce_or~2512 reduce_or~2460 reduce_or~2543 seg_data[1] } { 0.000ns 2.000ns 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}