lcd.map.rpt

CPLD开发板VHDL源程序并附上开发板的原理图

; char_ram.vhd                     ; yes             ; User VHDL File  ; F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/char_ram.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 141   ;
;     -- Combinational with no register       ; 100   ;
;     -- Register only                        ; 2     ;
;     -- Combinational with a register        ; 39    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 71    ;
;     -- 3 input functions                    ; 19    ;
;     -- 2 input functions                    ; 42    ;
;     -- 1 input functions                    ; 6     ;
;     -- 0 input functions                    ; 1     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 107   ;
;     -- arithmetic mode                      ; 34    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 26    ;
;     -- asynchronous clear/load mode         ; 41    ;
;                                             ;       ;
; Total registers                             ; 41    ;
; Total logic cells in carry chains           ; 38    ;
; I/O pins                                    ; 14    ;
; Maximum fan-out node                        ; Reset ;
; Maximum fan-out                             ; 41    ;
; Total fan-out                               ; 573   ;
; Average fan-out                             ; 3.70  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                  ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |lcd                       ; 141 (133)   ; 41           ; 0          ; 14   ; 0            ; 100 (92)     ; 2 (2)             ; 39 (39)          ; 38 (38)         ; 0 (0)      ; |lcd                ; work         ;
;    |char_ram:aa|           ; 8 (8)       ; 0            ; 0          ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |lcd|char_ram:aa    ; work         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; state[1,6,8,10]                       ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 4 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 41    ;
; Number of registers using Synchronous Clear  ; 26    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 41    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 12    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |lcd|div_counter[0]        ;
; 4:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |lcd|counter[2]            ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |lcd|char_addr[4]          ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |lcd|char_addr[0]          ;
; 6:1                ; 6 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; No         ; |lcd|data[2]~52            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Oct 11 20:55:58 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd -c lcd
Info: Found 1 design units, including 1 entities, in source file clklogic.gdf
    Info: Found entity 1: clklogic
Info: Found 2 design units, including 1 entities, in source file lcd.vhd
    Info: Found design unit 1: lcd-Behavioral
    Info: Found entity 1: lcd
Info: Found 2 design units, including 1 entities, in source file char_ram.vhd
    Info: Found design unit 1: char_ram-fun
    Info: Found entity 1: char_ram
Info: Elaborating entity "lcd" for the top level hierarchy
Info: Elaborating entity "char_ram" for hierarchy "char_ram:aa"
Warning: Reduced register "state[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "state[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "state[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "state[1]" with stuck data_in port to stuck value GND
Info: Implemented 155 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 12 output pins
    Info: Implemented 141 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Allocated 155 megabytes of memory during processing
    Info: Processing ended: Sat Oct 11 20:56:03 2008
    Info: Elapsed time: 00:00:05