lcd.tan.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "state\[0\] state\[0\] clk 972 ps " "Info: Found hold time violation between source  pin or register \"state\[0\]\" and destination pin or register \"state\[0\]\" for clock \"clk\" (Hold time is 972 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.050 ns + Largest " "Info: + Largest clock skew is 2.050 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 19.947 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 19.947 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 19 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 19; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkcnt\[6\] 2 REG LC_X5_Y3_N7 4 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X5_Y3_N7; Fanout = 4; REG Node = 'clkcnt\[6\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clkcnt[6] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(0.914 ns) 5.935 ns Equal0~182 3 COMB LC_X4_Y3_N8 1 " "Info: 3: + IC(1.297 ns) + CELL(0.914 ns) = 5.935 ns; Loc. = LC_X4_Y3_N8; Fanout = 1; COMB Node = 'Equal0~182'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.211 ns" { clkcnt[6] Equal0~182 } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.623 ns) + CELL(0.740 ns) 8.298 ns Equal0~185 4 COMB LC_X7_Y3_N1 1 " "Info: 4: + IC(1.623 ns) + CELL(0.740 ns) = 8.298 ns; Loc. = LC_X7_Y3_N1; Fanout = 1; COMB Node = 'Equal0~185'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { Equal0~182 Equal0~185 } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 8.803 ns rtl~0 5 COMB LC_X7_Y3_N2 20 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 8.803 ns; Loc. = LC_X7_Y3_N2; Fanout = 20; COMB Node = 'rtl~0'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Equal0~185 rtl~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(1.294 ns) 11.786 ns clkdiv 6 REG LC_X3_Y3_N2 3 " "Info: 6: + IC(1.689 ns) + CELL(1.294 ns) = 11.786 ns; Loc. = LC_X3_Y3_N2; Fanout = 3; REG Node = 'clkdiv'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { rtl~0 clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.201 ns) + CELL(1.294 ns) 16.281 ns clk_int 7 REG LC_X2_Y3_N2 21 " "Info: 7: + IC(3.201 ns) + CELL(1.294 ns) = 16.281 ns; Loc. = LC_X2_Y3_N2; Fanout = 21; REG Node = 'clk_int'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.495 ns" { clkdiv clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 19.947 ns state\[0\] 8 REG LC_X5_Y4_N9 6 " "Info: 8: + IC(2.748 ns) + CELL(0.918 ns) = 19.947 ns; Loc. = LC_X5_Y4_N9; Fanout = 6; REG Node = 'state\[0\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.666 ns" { clk_int state[0] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.817 ns ( 39.19 % ) " "Info: Total cell delay = 7.817 ns ( 39.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.130 ns ( 60.81 % ) " "Info: Total interconnect delay = 12.130 ns ( 60.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "19.947 ns" { clk clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int state[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "19.947 ns" { clk clk~combout clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int state[0] } { 0.000ns 0.000ns 1.267ns 1.297ns 1.623ns 0.305ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.740ns 0.200ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 17.897 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 17.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 19 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 19; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkcnt\[17\] 2 REG LC_X6_Y3_N8 4 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X6_Y3_N8; Fanout = 4; REG Node = 'clkcnt\[17\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clkcnt[17] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.518 ns) + CELL(0.511 ns) 6.753 ns rtl~0 3 COMB LC_X7_Y3_N2 20 " "Info: 3: + IC(2.518 ns) + CELL(0.511 ns) = 6.753 ns; Loc. = LC_X7_Y3_N2; Fanout = 20; COMB Node = 'rtl~0'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.029 ns" { clkcnt[17] rtl~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(1.294 ns) 9.736 ns clkdiv 4 REG LC_X3_Y3_N2 3 " "Info: 4: + IC(1.689 ns) + CELL(1.294 ns) = 9.736 ns; Loc. = LC_X3_Y3_N2; Fanout = 3; REG Node = 'clkdiv'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { rtl~0 clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.201 ns) + CELL(1.294 ns) 14.231 ns clk_int 5 REG LC_X2_Y3_N2 21 " "Info: 5: + IC(3.201 ns) + CELL(1.294 ns) = 14.231 ns; Loc. = LC_X2_Y3_N2; Fanout = 21; REG Node = 'clk_int'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.495 ns" { clkdiv clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 17.897 ns state\[0\] 6 REG LC_X5_Y4_N9 6 " "Info: 6: + IC(2.748 ns) + CELL(0.918 ns) = 17.897 ns; Loc. = LC_X5_Y4_N9; Fanout = 6; REG Node = 'state\[0\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.666 ns" { clk_int state[0] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.474 ns ( 36.17 % ) " "Info: Total cell delay = 6.474 ns ( 36.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.423 ns ( 63.83 % ) " "Info: Total interconnect delay = 11.423 ns ( 63.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "17.897 ns" { clk clkcnt[17] rtl~0 clkdiv clk_int state[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "17.897 ns" { clk clk~combout clkcnt[17] rtl~0 clkdiv clk_int state[0] } { 0.000ns 0.000ns 1.267ns 2.518ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.511ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "19.947 ns" { clk clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int state[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "19.947 ns" { clk clk~combout clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int state[0] } { 0.000ns 0.000ns 1.267ns 1.297ns 1.623ns 0.305ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.740ns 0.200ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "17.897 ns" { clk clkcnt[17] rtl~0 clkdiv clk_int state[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "17.897 ns" { clk clk~combout clkcnt[17] rtl~0 clkdiv clk_int state[0] } { 0.000ns 0.000ns 1.267ns 2.518ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.511ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.923 ns - Shortest register register " "Info: - Shortest register to register delay is 0.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[0\] 1 REG LC_X5_Y4_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N9; Fanout = 6; REG Node = 'state\[0\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { state[0] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.923 ns) 0.923 ns state\[0\] 2 REG LC_X5_Y4_N9 6 " "Info: 2: + IC(0.000 ns) + CELL(0.923 ns) = 0.923 ns; Loc. = LC_X5_Y4_N9; Fanout = 6; REG Node = 'state\[0\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.923 ns" { state[0] state[0] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.923 ns ( 100.00 % ) " "Info: Total cell delay = 0.923 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.923 ns" { state[0] state[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "0.923 ns" { state[0] state[0] } { 0.000ns 0.000ns } { 0.000ns 0.923ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "19.947 ns" { clk clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int state[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "19.947 ns" { clk clk~combout clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int state[0] } { 0.000ns 0.000ns 1.267ns 1.297ns 1.623ns 0.305ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.740ns 0.200ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "17.897 ns" { clk clkcnt[17] rtl~0 clkdiv clk_int state[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "17.897 ns" { clk clk~combout clkcnt[17] rtl~0 clkdiv clk_int state[0] } { 0.000ns 0.000ns 1.267ns 2.518ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.511ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.923 ns" { state[0] state[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "0.923 ns" { state[0] state[0] } { 0.000ns 0.000ns } { 0.000ns 0.923ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[2\] state\[4\] 37.144 ns register " "Info: tco from clock \"clk\" to destination pin \"data\[2\]\" through register \"state\[4\]\" is 37.144 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 19.947 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 19.947 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 19 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 19; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkcnt\[6\] 2 REG LC_X5_Y3_N7 4 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X5_Y3_N7; Fanout = 4; REG Node = 'clkcnt\[6\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clkcnt[6] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(0.914 ns) 5.935 ns Equal0~182 3 COMB LC_X4_Y3_N8 1 " "Info: 3: + IC(1.297 ns) + CELL(0.914 ns) = 5.935 ns; Loc. = LC_X4_Y3_N8; Fanout = 1; COMB Node = 'Equal0~182'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.211 ns" { clkcnt[6] Equal0~182 } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.623 ns) + CELL(0.740 ns) 8.298 ns Equal0~185 4 COMB LC_X7_Y3_N1 1 " "Info: 4: + IC(1.623 ns) + CELL(0.740 ns) = 8.298 ns; Loc. = LC_X7_Y3_N1; Fanout = 1; COMB Node = 'Equal0~185'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { Equal0~182 Equal0~185 } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 8.803 ns rtl~0 5 COMB LC_X7_Y3_N2 20 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 8.803 ns; Loc. = LC_X7_Y3_N2; Fanout = 20; COMB Node = 'rtl~0'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Equal0~185 rtl~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(1.294 ns) 11.786 ns clkdiv 6 REG LC_X3_Y3_N2 3 " "Info: 6: + IC(1.689 ns) + CELL(1.294 ns) = 11.786 ns; Loc. = LC_X3_Y3_N2; Fanout = 3; REG Node = 'clkdiv'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { rtl~0 clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.201 ns) + CELL(1.294 ns) 16.281 ns clk_int 7 REG LC_X2_Y3_N2 21 " "Info: 7: + IC(3.201 ns) + CELL(1.294 ns) = 16.281 ns; Loc. = LC_X2_Y3_N2; Fanout = 21; REG Node = 'clk_int'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.495 ns" { clkdiv clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 19.947 ns state\[4\] 8 REG LC_X6_Y4_N1 6 " "Info: 8: + IC(2.748 ns) + CELL(0.918 ns) = 19.947 ns; Loc. = LC_X6_Y4_N1; Fanout = 6; REG Node = 'state\[4\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.666 ns" { clk_int state[4] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.817 ns ( 39.19 % ) " "Info: Total cell delay = 7.817 ns ( 39.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.130 ns ( 60.81 % ) " "Info: Total interconnect delay = 12.130 ns ( 60.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan