📄 lcd.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "26 " "Warning: Found 26 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Equal0~184 " "Info: Detected gated clock \"Equal0~184\" as buffer" { } { { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~184" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[12\] " "Info: Detected ripple clock \"clkcnt\[12\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[12\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~183 " "Info: Detected gated clock \"Equal0~183\" as buffer" { } { { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~183" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[11\] " "Info: Detected ripple clock \"clkcnt\[11\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[11\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[9\] " "Info: Detected ripple clock \"clkcnt\[9\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[9\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[8\] " "Info: Detected ripple clock \"clkcnt\[8\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[8\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[10\] " "Info: Detected ripple clock \"clkcnt\[10\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[10\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~182 " "Info: Detected gated clock \"Equal0~182\" as buffer" { } { { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~182" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[7\] " "Info: Detected ripple clock \"clkcnt\[7\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[7\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[4\] " "Info: Detected ripple clock \"clkcnt\[4\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[5\] " "Info: Detected ripple clock \"clkcnt\[5\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[6\] " "Info: Detected ripple clock \"clkcnt\[6\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[6\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~181 " "Info: Detected gated clock \"Equal0~181\" as buffer" { } { { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~181" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[3\] " "Info: Detected ripple clock \"clkcnt\[3\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[2\] " "Info: Detected ripple clock \"clkcnt\[2\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[1\] " "Info: Detected ripple clock \"clkcnt\[1\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[0\] " "Info: Detected ripple clock \"clkcnt\[0\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[14\] " "Info: Detected ripple clock \"clkcnt\[14\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[14\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[13\] " "Info: Detected ripple clock \"clkcnt\[13\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[13\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[15\] " "Info: Detected ripple clock \"clkcnt\[15\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[15\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[17\] " "Info: Detected ripple clock \"clkcnt\[17\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[17\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[18\] " "Info: Detected ripple clock \"clkcnt\[18\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[18\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkcnt\[16\] " "Info: Detected ripple clock \"clkcnt\[16\]\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkcnt\[16\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "rtl~0 " "Info: Detected gated clock \"rtl~0\" as buffer" { } { { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~0" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkdiv " "Info: Detected ripple clock \"clkdiv\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkdiv" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_int " "Info: Detected ripple clock \"clk_int\" as buffer" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 110 -1 0 } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_int" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter\[1\] register counter\[4\] 98.26 MHz 10.177 ns Internal " "Info: Clock \"clk\" has Internal fmax of 98.26 MHz between source register \"counter\[1\]\" and destination register \"counter\[4\]\" (period= 10.177 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.418 ns + Longest register register " "Info: + Longest register to register delay is 7.418 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[1\] 1 REG LC_X5_Y2_N2 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N2; Fanout = 14; REG Node = 'counter\[1\]'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[1] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.425 ns) + CELL(0.511 ns) 1.936 ns data~1300 2 COMB LC_X5_Y2_N9 2 " "Info: 2: + IC(1.425 ns) + CELL(0.511 ns) = 1.936 ns; Loc. = LC_X5_Y2_N9; Fanout = 2; COMB Node = 'data~1300'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.936 ns" { counter[1] data~1300 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.734 ns) + CELL(0.200 ns) 2.870 ns LessThan6~84 3 COMB LC_X5_Y2_N0 5 " "Info: 3: + IC(0.734 ns) + CELL(0.200 ns) = 2.870 ns; Loc. = LC_X5_Y2_N0; Fanout = 5; COMB Node = 'LessThan6~84'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.934 ns" { data~1300 LessThan6~84 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 197 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.696 ns) + CELL(0.978 ns) 5.544 ns counter\[0\]~424 4 COMB LC_X5_Y2_N1 2 " "Info: 4: + IC(1.696 ns) + CELL(0.978 ns) = 5.544 ns; Loc. = LC_X5_Y2_N1; Fanout = 2; COMB Node = 'counter\[0\]~424'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.674 ns" { LessThan6~84 counter[0]~424 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 5.667 ns counter\[1\]~425 5 COMB LC_X5_Y2_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 5.667 ns; Loc. = LC_X5_Y2_N2; Fanout = 2; COMB Node = 'counter\[1\]~425'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { counter[0]~424 counter[1]~425 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 5.790 ns counter\[2\]~426 6 COMB LC_X5_Y2_N3 2 " "Info: 6: + IC(0.000 ns) + CELL(0.123 ns) = 5.790 ns; Loc. = LC_X5_Y2_N3; Fanout = 2; COMB Node = 'counter\[2\]~426'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { counter[1]~425 counter[2]~426 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 6.051 ns counter\[3\]~423 7 COMB LC_X5_Y2_N4 3 " "Info: 7: + IC(0.000 ns) + CELL(0.261 ns) = 6.051 ns; Loc. = LC_X5_Y2_N4; Fanout = 3; COMB Node = 'counter\[3\]~423'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { counter[2]~426 counter[3]~423 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.367 ns) 7.418 ns counter\[4\] 8 REG LC_X5_Y2_N5 16 " "Info: 8: + IC(0.000 ns) + CELL(1.367 ns) = 7.418 ns; Loc. = LC_X5_Y2_N5; Fanout = 16; REG Node = 'counter\[4\]'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.367 ns" { counter[3]~423 counter[4] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.563 ns ( 48.03 % ) " "Info: Total cell delay = 3.563 ns ( 48.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.855 ns ( 51.97 % ) " "Info: Total interconnect delay = 3.855 ns ( 51.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.418 ns" { counter[1] data~1300 LessThan6~84 counter[0]~424 counter[1]~425 counter[2]~426 counter[3]~423 counter[4] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "7.418 ns" { counter[1] data~1300 LessThan6~84 counter[0]~424 counter[1]~425 counter[2]~426 counter[3]~423 counter[4] } { 0.000ns 1.425ns 0.734ns 1.696ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.511ns 0.200ns 0.978ns 0.123ns 0.123ns 0.261ns 1.367ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.050 ns - Smallest " "Info: - Smallest clock skew is -2.050 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 17.897 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 17.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 19 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 19; CLK Node = 'clk'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkcnt\[17\] 2 REG LC_X6_Y3_N8 4 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X6_Y3_N8; Fanout = 4; REG Node = 'clkcnt\[17\]'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clkcnt[17] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.518 ns) + CELL(0.511 ns) 6.753 ns rtl~0 3 COMB LC_X7_Y3_N2 20 " "Info: 3: + IC(2.518 ns) + CELL(0.511 ns) = 6.753 ns; Loc. = LC_X7_Y3_N2; Fanout = 20; COMB Node = 'rtl~0'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.029 ns" { clkcnt[17] rtl~0 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(1.294 ns) 9.736 ns clkdiv 4 REG LC_X3_Y3_N2 3 " "Info: 4: + IC(1.689 ns) + CELL(1.294 ns) = 9.736 ns; Loc. = LC_X3_Y3_N2; Fanout = 3; REG Node = 'clkdiv'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { rtl~0 clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.201 ns) + CELL(1.294 ns) 14.231 ns clk_int 5 REG LC_X2_Y3_N2 21 " "Info: 5: + IC(3.201 ns) + CELL(1.294 ns) = 14.231 ns; Loc. = LC_X2_Y3_N2; Fanout = 21; REG Node = 'clk_int'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.495 ns" { clkdiv clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 110 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 17.897 ns counter\[4\] 6 REG LC_X5_Y2_N5 16 " "Info: 6: + IC(2.748 ns) + CELL(0.918 ns) = 17.897 ns; Loc. = LC_X5_Y2_N5; Fanout = 16; REG Node = 'counter\[4\]'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.666 ns" { clk_int counter[4] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.474 ns ( 36.17 % ) " "Info: Total cell delay = 6.474 ns ( 36.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.423 ns ( 63.83 % ) " "Info: Total interconnect delay = 11.423 ns ( 63.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "17.897 ns" { clk clkcnt[17] rtl~0 clkdiv clk_int counter[4] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "17.897 ns" { clk clk~combout clkcnt[17] rtl~0 clkdiv clk_int counter[4] } { 0.000ns 0.000ns 1.267ns 2.518ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.511ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 19.947 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 19.947 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 19 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 19; CLK Node = 'clk'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkcnt\[6\] 2 REG LC_X5_Y3_N7 4 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X5_Y3_N7; Fanout = 4; REG Node = 'clkcnt\[6\]'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clkcnt[6] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(0.914 ns) 5.935 ns Equal0~182 3 COMB LC_X4_Y3_N8 1 " "Info: 3: + IC(1.297 ns) + CELL(0.914 ns) = 5.935 ns; Loc. = LC_X4_Y3_N8; Fanout = 1; COMB Node = 'Equal0~182'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.211 ns" { clkcnt[6] Equal0~182 } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.623 ns) + CELL(0.740 ns) 8.298 ns Equal0~185 4 COMB LC_X7_Y3_N1 1 " "Info: 4: + IC(1.623 ns) + CELL(0.740 ns) = 8.298 ns; Loc. = LC_X7_Y3_N1; Fanout = 1; COMB Node = 'Equal0~185'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { Equal0~182 Equal0~185 } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 8.803 ns rtl~0 5 COMB LC_X7_Y3_N2 20 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 8.803 ns; Loc. = LC_X7_Y3_N2; Fanout = 20; COMB Node = 'rtl~0'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Equal0~185 rtl~0 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(1.294 ns) 11.786 ns clkdiv 6 REG LC_X3_Y3_N2 3 " "Info: 6: + IC(1.689 ns) + CELL(1.294 ns) = 11.786 ns; Loc. = LC_X3_Y3_N2; Fanout = 3; REG Node = 'clkdiv'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { rtl~0 clkdiv } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 75 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.201 ns) + CELL(1.294 ns) 16.281 ns clk_int 7 REG LC_X2_Y3_N2 21 " "Info: 7: + IC(3.201 ns) + CELL(1.294 ns) = 16.281 ns; Loc. = LC_X2_Y3_N2; Fanout = 21; REG Node = 'clk_int'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.495 ns" { clkdiv clk_int } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 110 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 19.947 ns counter\[1\] 8 REG LC_X5_Y2_N2 14 " "Info: 8: + IC(2.748 ns) + CELL(0.918 ns) = 19.947 ns; Loc. = LC_X5_Y2_N2; Fanout = 14; REG Node = 'counter\[1\]'" { } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.666 ns" { clk_int counter[1] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.817 ns ( 39.19 % ) " "Info: Total cell delay = 7.817 ns ( 39.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.130 ns ( 60.81 % ) " "Info: Total interconnect delay = 12.130 ns ( 60.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "19.947 ns" { clk clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int counter[1] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "19.947 ns" { clk clk~combout clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int counter[1] } { 0.000ns 0.000ns 1.267ns 1.297ns 1.623ns 0.305ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.740ns 0.200ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "17.897 ns" { clk clkcnt[17] rtl~0 clkdiv clk_int counter[4] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "17.897 ns" { clk clk~combout clkcnt[17] rtl~0 clkdiv clk_int counter[4] } { 0.000ns 0.000ns 1.267ns 2.518ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.511ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "19.947 ns" { clk clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int counter[1] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "19.947 ns" { clk clk~combout clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int counter[1] } { 0.000ns 0.000ns 1.267ns 1.297ns 1.623ns 0.305ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.740ns 0.200ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.418 ns" { counter[1] data~1300 LessThan6~84 counter[0]~424 counter[1]~425 counter[2]~426 counter[3]~423 counter[4] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "7.418 ns" { counter[1] data~1300 LessThan6~84 counter[0]~424 counter[1]~425 counter[2]~426 counter[3]~423 counter[4] } { 0.000ns 1.425ns 0.734ns 1.696ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.511ns 0.200ns 0.978ns 0.123ns 0.123ns 0.261ns 1.367ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "17.897 ns" { clk clkcnt[17] rtl~0 clkdiv clk_int counter[4] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "17.897 ns" { clk clk~combout clkcnt[17] rtl~0 clkdiv clk_int counter[4] } { 0.000ns 0.000ns 1.267ns 2.518ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.511ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "19.947 ns" { clk clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int counter[1] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "19.947 ns" { clk clk~combout clkcnt[6] Equal0~182 Equal0~185 rtl~0 clkdiv clk_int counter[1] } { 0.000ns 0.000ns 1.267ns 1.297ns 1.623ns 0.305ns 1.689ns 3.201ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.740ns 0.200ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
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