lcd.fit.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "18.741 ns register pin " "Info: Estimated most critical path is register to pin delay of 18.741 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[0\] 1 REG LAB_X5_Y2 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y2; Fanout = 13; REG Node = 'counter\[0\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[0] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.003 ns) + CELL(0.978 ns) 2.981 ns Add1~102 2 COMB LAB_X3_Y2 2 " "Info: 2: + IC(2.003 ns) + CELL(0.978 ns) = 2.981 ns; Loc. = LAB_X3_Y2; Fanout = 2; COMB Node = 'Add1~102'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.981 ns" { counter[0] Add1~102 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 3.104 ns Add1~104 3 COMB LAB_X3_Y2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 3.104 ns; Loc. = LAB_X3_Y2; Fanout = 2; COMB Node = 'Add1~104'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add1~102 Add1~104 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 3.227 ns Add1~106 4 COMB LAB_X3_Y2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 3.227 ns; Loc. = LAB_X3_Y2; Fanout = 2; COMB Node = 'Add1~106'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add1~104 Add1~106 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 3.626 ns Add1~108 5 COMB LAB_X3_Y2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.399 ns) = 3.626 ns; Loc. = LAB_X3_Y2; Fanout = 2; COMB Node = 'Add1~108'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.399 ns" { Add1~106 Add1~108 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 4.860 ns Add1~109 6 COMB LAB_X3_Y2 1 " "Info: 6: + IC(0.000 ns) + CELL(1.234 ns) = 4.860 ns; Loc. = LAB_X3_Y2; Fanout = 1; COMB Node = 'Add1~109'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { Add1~108 Add1~109 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.115 ns) + CELL(0.740 ns) 7.715 ns Add2~454 7 COMB LAB_X5_Y1 2 " "Info: 7: + IC(2.115 ns) + CELL(0.740 ns) = 7.715 ns; Loc. = LAB_X5_Y1; Fanout = 2; COMB Node = 'Add2~454'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { Add1~109 Add2~454 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 8.895 ns char_addr\[5\]~1820 8 COMB LAB_X5_Y1 1 " "Info: 8: + IC(0.980 ns) + CELL(0.200 ns) = 8.895 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = 'char_addr\[5\]~1820'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { Add2~454 char_addr[5]~1820 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 10.075 ns char_addr\[5\]~1821 9 COMB LAB_X5_Y1 1 " "Info: 9: + IC(0.980 ns) + CELL(0.200 ns) = 10.075 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = 'char_addr\[5\]~1821'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { char_addr[5]~1820 char_addr[5]~1821 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 11.255 ns char_addr\[5\]~1822 10 COMB LAB_X5_Y1 4 " "Info: 10: + IC(0.980 ns) + CELL(0.200 ns) = 11.255 ns; Loc. = LAB_X5_Y1; Fanout = 4; COMB Node = 'char_addr\[5\]~1822'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { char_addr[5]~1821 char_addr[5]~1822 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 12.435 ns data\[1\]~1303 11 COMB LAB_X5_Y1 5 " "Info: 11: + IC(0.980 ns) + CELL(0.200 ns) = 12.435 ns; Loc. = LAB_X5_Y1; Fanout = 5; COMB Node = 'data\[1\]~1303'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { char_addr[5]~1822 data[1]~1303 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 13.615 ns data\[1\]~1323 12 COMB LAB_X5_Y1 2 " "Info: 12: + IC(0.980 ns) + CELL(0.200 ns) = 13.615 ns; Loc. = LAB_X5_Y1; Fanout = 2; COMB Node = 'data\[1\]~1323'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { data[1]~1303 data[1]~1323 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.497 ns) + CELL(0.740 ns) 15.852 ns data\[4\]~1314 13 COMB LAB_X3_Y1 1 " "Info: 13: + IC(1.497 ns) + CELL(0.740 ns) = 15.852 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'data\[4\]~1314'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.237 ns" { data[1]~1323 data[4]~1314 } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(2.322 ns) 18.741 ns data\[4\] 14 PIN PIN_30 0 " "Info: 14: + IC(0.567 ns) + CELL(2.322 ns) = 18.741 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'data\[4\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.889 ns" { data[4]~1314 data[4] } "NODE_NAME" } } { "lcd.vhd" "" { Text "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.659 ns ( 40.87 % ) " "Info: Total cell delay = 7.659 ns ( 40.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.082 ns ( 59.13 % ) " "Info: Total interconnect delay = 11.082 ns ( 59.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "18.741 ns" { counter[0] Add1~102 Add1~104 Add1~106 Add1~108 Add1~109 Add2~454 char_addr[5]~1820 char_addr[5]~1821 char_addr[5]~1822 data[1]~1303 data[1]~1323 data[4]~1314 data[4] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "8 8 " "Info: Average interconnect usage is 8% of the available device resources. Peak interconnect usage is 8%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X8_Y5 " "Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.fit.smsg " "Info: Generated suppressed messages file F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Info: Allocated 171 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 11 20:56:15 2008 " "Info: Processing ended: Sat Oct 11 20:56:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}