lcd.fit.rpt

CPLD开发板VHDL源程序并附上开发板的原理图

; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:16            ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:12;1:4        ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:8;1:1;2:6;3:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:8;1:6;2:2     ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:16            ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:8;1:8         ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:12;1:4        ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 1:16            ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:14;1:2        ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:16            ;
; LEs in Chains - Fit Attempt 1                                                  ; 38              ;
; LEs in Long Chains - Fit Attempt 1                                             ; 19              ;
; LABs with Chains - Fit Attempt 1                                               ; 5               ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0               ;
; Time - Fit Attempt 1                                                           ; 1               ;
+--------------------------------------------------------------------------------+-----------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1      ; 7      ;
; Early Slack - Fit Attempt 1         ; -41348 ;
; Mid Wire Use - Fit Attempt 1        ; 14     ;
; Mid Slack - Fit Attempt 1           ; -38651 ;
; Late Wire Use - Fit Attempt 1       ; 15     ;
; Late Slack - Fit Attempt 1          ; -38651 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000  ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.188  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -33279 ;
; Early Wire Use - Fit Attempt 1      ; 9      ;
; Peak Regional Wire - Fit Attempt 1  ; 8      ;
; Mid Slack - Fit Attempt 1           ; -36761 ;
; Late Slack - Fit Attempt 1          ; -36761 ;
; Late Slack - Fit Attempt 1          ; -36761 ;
; Late Wire Use - Fit Attempt 1       ; 14     ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.171  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Oct 11 20:56:05 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lcd -c lcd
Info: Selected device EPM240T100C5 for design "lcd"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Warning: No exact pin location assignment(s) for 14 pins of 14 total pins
    Info: Pin lcd_rs not assigned to an exact location on the device
    Info: Pin lcd_rw not assigned to an exact location on the device
    Info: Pin lcd_e not assigned to an exact location on the device
    Info: Pin data[0] not assigned to an exact location on the device
    Info: Pin data[1] not assigned to an exact location on the device
    Info: Pin data[2] not assigned to an exact location on the device
    Info: Pin data[3] not assigned to an exact location on the device
    Info: Pin data[4] not assigned to an exact location on the device
    Info: Pin data[5] not assigned to an exact location on the device
    Info: Pin data[6] not assigned to an exact location on the device
    Info: Pin data[7] not assigned to an exact location on the device
    Info: Pin clk_out not assigned to an exact location on the device
    Info: Pin Reset not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 14
Info: Automatically promoted some destinations of signal "clk_int" to use Global clock
    Info: Destination "clk_out" may be non-global or may not use global clock
    Info: Destination "clk_int" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "clkdiv" to use Global clock
    Info: Destination "clkdiv" may be non-global or may not use global clock
Info: Automatically promoted signal "Reset" to use Global clock in PIN 12
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 12 (unused VREF, 3.30 VCCIO, 0 input, 12 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  36 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to pin delay of 18.741 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y2; Fanout = 13; REG Node = 'counter[0]'
    Info: 2: + IC(2.003 ns) + CELL(0.978 ns) = 2.981 ns; Loc. = LAB_X3_Y2; Fanout = 2; COMB Node = 'Add1~102'
    Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 3.104 ns; Loc. = LAB_X3_Y2; Fanout = 2; COMB Node = 'Add1~104'
    Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 3.227 ns; Loc. = LAB_X3_Y2; Fanout = 2; COMB Node = 'Add1~106'
    Info: 5: + IC(0.000 ns) + CELL(0.399 ns) = 3.626 ns; Loc. = LAB_X3_Y2; Fanout = 2; COMB Node = 'Add1~108'
    Info: 6: + IC(0.000 ns) + CELL(1.234 ns) = 4.860 ns; Loc. = LAB_X3_Y2; Fanout = 1; COMB Node = 'Add1~109'
    Info: 7: + IC(2.115 ns) + CELL(0.740 ns) = 7.715 ns; Loc. = LAB_X5_Y1; Fanout = 2; COMB Node = 'Add2~454'
    Info: 8: + IC(0.980 ns) + CELL(0.200 ns) = 8.895 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = 'char_addr[5]~1820'
    Info: 9: + IC(0.980 ns) + CELL(0.200 ns) = 10.075 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = 'char_addr[5]~1821'
    Info: 10: + IC(0.980 ns) + CELL(0.200 ns) = 11.255 ns; Loc. = LAB_X5_Y1; Fanout = 4; COMB Node = 'char_addr[5]~1822'
    Info: 11: + IC(0.980 ns) + CELL(0.200 ns) = 12.435 ns; Loc. = LAB_X5_Y1; Fanout = 5; COMB Node = 'data[1]~1303'
    Info: 12: + IC(0.980 ns) + CELL(0.200 ns) = 13.615 ns; Loc. = LAB_X5_Y1; Fanout = 2; COMB Node = 'data[1]~1323'
    Info: 13: + IC(1.497 ns) + CELL(0.740 ns) = 15.852 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'data[4]~1314'
    Info: 14: + IC(0.567 ns) + CELL(2.322 ns) = 18.741 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'data[4]'
    Info: Total cell delay = 7.659 ns ( 40.87 % )
    Info: Total interconnect delay = 11.082 ns ( 59.13 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 8% of the available device resources. Peak interconnect usage is 8%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:01
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 171 megabytes of memory during processing
    Info: Processing ended: Sat Oct 11 20:56:15 2008
    Info: Elapsed time: 00:00:10


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/学习文件/EDA资料/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/接口实验/lcd液晶显示/lcd/lcd.fit.smsg.