lcd.fit.eqn

CPLD开发板VHDL源程序并附上开发板的原理图

--clk_int is clk_int at LC99
clk_int_reg_input = VCC;
clk_int = TFFE(clk_int_reg_input, clkdiv, GLOBAL(Reset), , );


--A1L301Q is lcd_e~reg0 at LC65
A1L301Q_reg_input = VCC;
A1L301Q = TFFE(A1L301Q_reg_input, !clkdiv, GLOBAL(Reset), , );


--flag is flag at LC79
flag_p1_out = !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !flag;
flag_or_out = flag_p1_out;
flag_reg_input = flag_or_out;
flag = TFFE(flag_reg_input, clk_int, GLOBAL(Reset), , );


--state[5] is state[5] at LC66
state[5]_p1_out = !flag & !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4];
state[5]_or_out = state[5]_p1_out;
state[5]_reg_input = state[5]_or_out;
state[5] = DFFE(state[5]_reg_input, clk_int, GLOBAL(Reset), , );


--D1_dffs[0] is lpm_counter:div_counter_rtl_0|dffs[0] at LC96
D1_dffs[0]_p1_out = flag & !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4];
D1_dffs[0]_p2_out = !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & D1_dffs[0];
D1_dffs[0]_or_out = D1_dffs[0]_p1_out # D1_dffs[0]_p2_out;
D1_dffs[0]_reg_input = D1_dffs[0]_or_out;
D1_dffs[0] = TFFE(D1_dffs[0]_reg_input, clk_int, GLOBAL(Reset), , );


--counter[6] is counter[6] at LC86
counter[6]_p1_out = counter[5] & counter[4] & counter[3] & counter[2] & counter[1] & counter[0] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !counter[6];
counter[6]_p2_out = !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & counter[6] & !flag;
counter[6]_or_out = counter[6]_p1_out # counter[6]_p2_out;
counter[6]_reg_input = counter[6]_or_out;
counter[6] = TFFE(counter[6]_reg_input, clk_int, GLOBAL(Reset), , );


--D1_dffs[1] is lpm_counter:div_counter_rtl_0|dffs[1] at LC93
D1_dffs[1]_p1_out = flag & !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & D1_dffs[0] & !state[4];
D1_dffs[1]_p2_out = !flag & !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & D1_dffs[1];
D1_dffs[1]_or_out = D1_dffs[1]_p1_out # D1_dffs[1]_p2_out;
D1_dffs[1]_reg_input = D1_dffs[1]_or_out;
D1_dffs[1] = TFFE(D1_dffs[1]_reg_input, clk_int, GLOBAL(Reset), , );


--D1_dffs[2] is lpm_counter:div_counter_rtl_0|dffs[2] at LC94
D1_dffs[2]_p1_out = flag & D1_dffs[1] & !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & D1_dffs[0] & !state[4];
D1_dffs[2]_p2_out = !flag & !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & D1_dffs[2];
D1_dffs[2]_or_out = D1_dffs[2]_p1_out # D1_dffs[2]_p2_out;
D1_dffs[2]_reg_input = D1_dffs[2]_or_out;
D1_dffs[2] = TFFE(D1_dffs[2]_reg_input, clk_int, GLOBAL(Reset), , );


--counter[0] is counter[0] at LC87
counter[0]_p0_out = state[9] & !state[7] & !state[0] & !state[2] & !state[3] & !state[5] & !state[4] & !counter[6];
counter[0]_p1_out = !counter[3] & !counter[2] & !counter[1] & !counter[5] & state[9] & !state[7] & !state[0] & !state[2] & !state[3] & !state[5] & !counter[0] & !state[4];
counter[0]_p2_out = !state[9] & !state[7] & !state[0] & !state[2] & !state[3] & !state[5] & counter[0] & !state[4] & !flag;
counter[0]_p4_out = !counter[5] & state[9] & !state[7] & !state[0] & !state[2] & !state[3] & !state[5] & !state[4] & !counter[4];
counter[0]_or_out = counter[0]_p0_out # counter[0]_p1_out # counter[0]_p2_out # counter[0]_p4_out;
counter[0]_reg_input = counter[0]_or_out;
counter[0] = TFFE(counter[0]_reg_input, clk_int, GLOBAL(Reset), , );


--D1_dffs[3] is lpm_counter:div_counter_rtl_0|dffs[3] at LC95
D1_dffs[3]_p1_out = flag & D1_dffs[2] & D1_dffs[1] & !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & D1_dffs[0] & !state[4];
D1_dffs[3]_p2_out = !flag & !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & D1_dffs[3];
D1_dffs[3]_or_out = D1_dffs[3]_p1_out # D1_dffs[3]_p2_out;
D1_dffs[3]_reg_input = D1_dffs[3]_or_out;
D1_dffs[3] = TFFE(D1_dffs[3]_reg_input, clk_int, GLOBAL(Reset), , );


--counter[1] is counter[1] at LC68
counter[1]_p1_out = !counter[5] & !counter[4] & counter[0] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4];
counter[1]_p2_out = counter[0] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !counter[6];
counter[1]_p4_out = !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !flag & counter[1];
counter[1]_or_out = counter[1]_p1_out # counter[1]_p2_out # counter[1]_p4_out;
counter[1]_reg_input = counter[1]_or_out;
counter[1] = TFFE(counter[1]_reg_input, clk_int, GLOBAL(Reset), , );


--state[4] is state[4] at LC82
state[4]_p0_out = !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & flag & D1_dffs[3] & D1_dffs[2] & D1_dffs[1] & D1_dffs[0];
state[4]_p1_out = counter[2] & counter[6] & counter[4] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4];
state[4]_p2_out = counter[6] & counter[4] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & counter[1];
state[4]_p4_out = counter[6] & counter[4] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & counter[0];
state[4]_or_out = A1L311 # state[4]_p0_out # state[4]_p1_out # state[4]_p2_out # state[4]_p4_out;
state[4]_reg_input = state[4]_or_out;
state[4] = DFFE(state[4]_reg_input, clk_int, GLOBAL(Reset), , );


--counter[2] is counter[2] at LC88
counter[2]_p1_out = !counter[5] & !counter[4] & counter[1] & counter[0] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4];
counter[2]_p2_out = counter[1] & counter[0] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !counter[6];
counter[2]_p4_out = !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !flag & counter[2];
counter[2]_or_out = counter[2]_p1_out # counter[2]_p2_out # counter[2]_p4_out;
counter[2]_reg_input = counter[2]_or_out;
counter[2] = TFFE(counter[2]_reg_input, clk_int, GLOBAL(Reset), , );


--counter[3] is counter[3] at LC89
counter[3]_p1_out = !counter[5] & !counter[4] & counter[2] & counter[1] & counter[0] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4];
counter[3]_p2_out = counter[2] & counter[1] & counter[0] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !counter[6];
counter[3]_p4_out = !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !flag & counter[3];
counter[3]_or_out = counter[3]_p1_out # counter[3]_p2_out # counter[3]_p4_out;
counter[3]_reg_input = counter[3]_or_out;
counter[3] = TFFE(counter[3]_reg_input, clk_int, GLOBAL(Reset), , );


--counter[4] is counter[4] at LC90
counter[4]_p1_out = !counter[5] & counter[3] & counter[2] & counter[1] & counter[0] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !counter[4];
counter[4]_p2_out = counter[3] & counter[2] & counter[1] & counter[0] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !counter[6];
counter[4]_p4_out = !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & counter[4] & !flag;
counter[4]_or_out = counter[4]_p1_out # counter[4]_p2_out # counter[4]_p4_out;
counter[4]_reg_input = counter[4]_or_out;
counter[4] = TFFE(counter[4]_reg_input, clk_int, GLOBAL(Reset), , );


--counter[5] is counter[5] at LC91
counter[5]_p1_out = counter[4] & counter[3] & counter[2] & counter[1] & counter[0] & !counter[6] & state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4];
counter[5]_p2_out = !state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !flag & counter[5];
counter[5]_or_out = counter[5]_p1_out # counter[5]_p2_out;
counter[5]_reg_input = counter[5]_or_out;
counter[5] = TFFE(counter[5]_reg_input, clk_int, GLOBAL(Reset), , );


--state[7] is state[7] at LC92
state[7]_p1_out = state[9] & !state[5] & !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & counter[5] & counter[3] & !counter[6] & !counter[4] & !counter[2] & !counter[1] & !counter[0];
state[7]_or_out = state[7]_p1_out;
state[7]_reg_input = state[7]_or_out;
state[7] = DFFE(state[7]_reg_input, clk_int, GLOBAL(Reset), , );


--state[3] is state[3] at LC50
state[3]_p1_out = state[5] & !state[7] & !state[4] & !state[9] & !state[3] & !state[2] & !state[0];
state[3]_or_out = state[3]_p1_out;
state[3]_reg_input = state[3]_or_out;
state[3] = DFFE(state[3]_reg_input, clk_int, GLOBAL(Reset), , );


--state[0] is state[0] at LC59
state[0]_p1_out = state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !state[9] & !state[5];
state[0]_or_out = state[0]_p1_out;
state[0]_reg_input = state[0]_or_out;
state[0] = DFFE(state[0]_reg_input, clk_int, GLOBAL(Reset), , );


--state[2] is state[2] at LC60
state[2]_p1_out = !state[3] & !state[2] & state[0] & !state[7] & !state[4] & !state[9] & !state[5];
state[2]_or_out = state[2]_p1_out;
state[2]_reg_input = state[2]_or_out;
state[2] = DFFE(state[2]_reg_input, clk_int, GLOBAL(Reset), , );


--A1L26 is data~2408 at LC67
A1L26_p1_out = state[7] & !state[4] & !state[5] & !state[9] & !state[3] & !state[2] & !state[0];
A1L26_or_out = A1L26_p1_out;
A1L26 = A1L26_or_out;


--A1L36 is data~2414 at LC48
A1L36_p0_out = !state[3] & !state[2] & state[0] & !state[7] & !state[4] & !state[9] & !state[5];
A1L36_p1_out = state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !state[9] & !state[5];
A1L36_p2_out = !state[3] & !state[2] & !state[0] & !state[7] & !state[4] & !state[9] & state[5];
A1L36_p3_out = !state[3] & !state[2] & !state[0] & !state[7] & state[4] & !state[9] & !state[5];
A1L36_p4_out = !state[3] & state[2] & !state[0] & !state[7] & !state[4] & !state[9] & !state[5];
A1L36_or_out = A1L58 # A1L36_p0_out # A1L36_p1_out # A1L36_p2_out # A1L36_p3_out # A1L36_p4_out;
A1L36 = A1L36_or_out;


--state[9] is state[9] at LC85
state[9]_p0_out = !state[3] & state[2] & !state[0] & !state[7] & !state[4] & !state[9] & !state[5];