buzzer.tan.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 12 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register clk_div2\[10\] register out_bit_tmp 45.45 MHz 22.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 45.45 MHz between source register \"clk_div2\[10\]\" and destination register \"out_bit_tmp\" (period= 22.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.000 ns + Longest register register " "Info: + Longest register to register delay is 17.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_div2\[10\] 1 REG LC23 67 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC23; Fanout = 67; REG Node = 'clk_div2\[10\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "" { clk_div2[10] } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns Mux~9700 2 COMB LC32 2 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC32; Fanout = 2; COMB Node = 'Mux~9700'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "9.000 ns" { clk_div2[10] Mux~9700 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 17.000 ns out_bit_tmp 3 REG LC3 13 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 17.000 ns; Loc. = LC3; Fanout = 13; REG Node = 'out_bit_tmp'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "8.000 ns" { Mux~9700 out_bit_tmp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns 76.47 % " "Info: Total cell delay = 13.000 ns ( 76.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 23.53 % " "Info: Total interconnect delay = 4.000 ns ( 23.53 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "17.000 ns" { clk_div2[10] Mux~9700 out_bit_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "17.000 ns" { clk_div2[10] Mux~9700 out_bit_tmp } { 0.000ns 2.000ns 2.000ns } { 0.000ns 7.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 43 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 43; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "" { clk } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns out_bit_tmp 2 REG LC3 13 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 13; REG Node = 'out_bit_tmp'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "0.000 ns" { clk out_bit_tmp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "3.000 ns" { clk out_bit_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out out_bit_tmp } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 43 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 43; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "" { clk } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clk_div2\[10\] 2 REG LC23 67 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC23; Fanout = 67; REG Node = 'clk_div2\[10\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "0.000 ns" { clk clk_div2[10] } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "3.000 ns" { clk clk_div2[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out clk_div2[10] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "3.000 ns" { clk out_bit_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out out_bit_tmp } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "3.000 ns" { clk clk_div2[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out clk_div2[10] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "17.000 ns" { clk_div2[10] Mux~9700 out_bit_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "17.000 ns" { clk_div2[10] Mux~9700 out_bit_tmp } { 0.000ns 2.000ns 2.000ns } { 0.000ns 7.000ns 6.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "3.000 ns" { clk out_bit_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out out_bit_tmp } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "3.000 ns" { clk clk_div2[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out clk_div2[10] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out_bit out_bit_tmp 8.000 ns register " "Info: tco from clock \"clk\" to destination pin \"out_bit\" through register \"out_bit_tmp\" is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 43 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 43; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "" { clk } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns out_bit_tmp 2 REG LC3 13 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 13; REG Node = 'out_bit_tmp'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "0.000 ns" { clk out_bit_tmp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "3.000 ns" { clk out_bit_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out out_bit_tmp } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out_bit_tmp 1 REG LC3 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 13; REG Node = 'out_bit_tmp'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "" { out_bit_tmp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns out_bit 2 PIN PIN_12 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'out_bit'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "4.000 ns" { out_bit_tmp out_bit } "NODE_NAME" } "" } } { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "4.000 ns" { out_bit_tmp out_bit } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { out_bit_tmp out_bit } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "3.000 ns" { clk out_bit_tmp } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out out_bit_tmp } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer_cmp.qrpt" Compiler "buzzer" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/db/buzzer.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/" "" "4.000 ns" { out_bit_tmp out_bit } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { out_bit_tmp out_bit } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 21 17:15:38 2005 " "Info: Processing ended: Mon Nov 21 17:15:38 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}