📄 buzzer.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 21 17:14:59 2005 " "Info: Processing started: Mon Nov 21 17:14:59 2005" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off buzzer -c buzzer " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off buzzer -c buzzer" { } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "buzzer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file buzzer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 buzzer-arch " "Info: Found design unit 1: buzzer-arch" { } { { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 17 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 buzzer " "Info: Found entity 1: buzzer" { } { { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 10 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "buzzer " "Info: Elaborating entity \"buzzer\" for the top level hierarchy" { } { } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "buzzer.vhd(150) " "Info: VHDL Case Statement information at buzzer.vhd(150): OTHERS choice is never selected" { } { { "buzzer.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 150 0 0 } } } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt\[0\]~22 22 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=22) from the following logic: \"cnt\[0\]~22\"" { } { { "buzzer.vhd" "cnt\[0\]~22" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/蜂鸣器/buzzer.vhd" 22 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" { } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" { } { { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" { } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" { } { { "look_add.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" { } { { "altshift.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } } } 0} } { } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "13 " "Info: Ignored 13 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "13 " "Info: Ignored 13 SOFT buffer(s)" { } { } 0} } { } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" { } { } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" { } { } 0} } { } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "74 " "Info: Implemented 74 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" { } { } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" { } { } 0} { "Info" "ISCL_SCL_TM_MCELLS" "64 " "Info: Implemented 64 macrocells" { } { } 0} { "Info" "ISCL_SCL_TM_SEXPS" "7 " "Info: Implemented 7 shareable expanders" { } { } 0} } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 21 17:15:22 2005 " "Info: Processing ended: Mon Nov 21 17:15:22 2005" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Info: Elapsed time: 00:00:24" { } { } 0} } { } 0}
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