dial2.vhd

CPLD开发板VHDL源程序并附上开发板的原理图

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY dial2 IS
   PORT (
      clk                     : IN std_logic;   
      rst                     : IN std_logic;   
      datain                  : IN std_logic_vector(7 downto 0);
      dataout                 : OUT std_logic_vector(7 DOWNTO 0);   --各段数据输出  
      en                      : OUT std_logic_vector(7 DOWNTO 0));  --COM使能输出 
END dial2;

ARCHITECTURE arch OF dial2 IS
signal cnt_scan : std_logic_vector(15 downto 0 );
signal data4 :    std_logic_vector(3 downto 0);
signal dataout_xhdl1 : std_logic_vector(7 downto 0);
signal en_xhdl : std_logic_vector(7 downto 0);
begin

 dataout<=dataout_xhdl1;
 en<= en_xhdl;
 
 process(clk,rst)
 begin
   if(rst='0')then 
   cnt_scan<="0000000000000000";
   elsif(clk'event and clk='1')then
   cnt_scan<=cnt_scan+1;
   end if;
 end process;

 
 process(cnt_scan(15 downto 13))
 begin
 case cnt_scan(15 downto 13) is
     when"000"=> en_xhdl<="11111110";
     when"001"=> en_xhdl<="11111101";
     when"010"=> en_xhdl<="11111011";
     when"011"=> en_xhdl<="11110111";
     when"100"=> en_xhdl<="11101111";
     when"101"=> en_xhdl<="11011111";
     when"110"=> en_xhdl<="10111111";
     when"111"=> en_xhdl<="01111111";
     when others=> en_xhdl<="11111110";
  end case;

 end process;

process(en_xhdl,datain)
begin
 case en_xhdl is
   when "11111110"=> data4<="000"&datain(0);
   when "11111101"=> data4<="000"&datain(1);
   when "11111011"=> data4<="000"&datain(2);
   when "11110111"=> data4<="000"&datain(3);
   when "11101111"=> data4<="000"&datain(4);
   when "11011111"=> data4<="000"&datain(5);
   when "10111111"=> data4<="000"&datain(6);
   when "01111111"=> data4<="000"&datain(7);
   when others => data4<="1000";
  end case;
end process;

process(data4)
begin
  case data4 is
   WHEN "0000" =>
                  dataout_xhdl1 <= "00000011";    
         WHEN "0001" =>
                  dataout_xhdl1 <= "10011111";    
         WHEN "0010" =>
                  dataout_xhdl1 <= "00100101";    
         WHEN "0011" =>
                  dataout_xhdl1 <= "00001101";    
         WHEN "0100" =>
                  dataout_xhdl1 <= "10011001";    
         WHEN "0101" =>
                  dataout_xhdl1 <= "01001001";    
         WHEN "0110" =>
                  dataout_xhdl1 <= "01000001";    
         WHEN "0111" =>
                  dataout_xhdl1 <= "00011111";    
         WHEN "1000" =>
                  dataout_xhdl1 <= "00000001";    
         WHEN "1001" =>
                  dataout_xhdl1 <= "00011001";    
         WHEN "1010" =>
                  dataout_xhdl1 <= "00010001";    
         WHEN "1011" =>
                  dataout_xhdl1 <= "11000001";    
         WHEN "1100" =>
                  dataout_xhdl1 <= "01100011";    
         WHEN "1101" =>
                  dataout_xhdl1 <= "10000101";    
         WHEN "1110" =>
                  dataout_xhdl1 <= "01100001";    
         WHEN "1111" =>
                  dataout_xhdl1 <= "01110001";    
         WHEN OTHERS =>
                  NULL;
         
      END CASE;
   END PROCESS;
   
end arch;