dial2.map.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 20 16:01:40 2006 " "Info: Processing started: Thu Apr 20 16:01:40 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dial2 -c dial2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dial2 -c dial2" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dial2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dial2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dial2-arch " "Info: Found design unit 1: dial2-arch" {  } { { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 dial2 " "Info: Found entity 1: dial2" {  } { { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dial2 " "Info: Elaborating entity \"dial2\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "dial2.vhd(46) " "Info: VHDL Case Statement information at dial2.vhd(46): OTHERS choice is never selected" {  } { { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 46 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "dial2.vhd(101) " "Info: VHDL Case Statement information at dial2.vhd(101): OTHERS choice is never selected" {  } { { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 101 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_scan\[0\]~0 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_scan\[0\]~0\"" {  } { { "dial2.vhd" "cnt_scan\[0\]~0" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[1\] VCC " "Warning: Pin \"dataout\[1\]\" stuck at VCC" {  } { { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[5\] GND " "Warning: Pin \"dataout\[5\]\" stuck at GND" {  } { { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[6\] GND " "Warning: Pin \"dataout\[6\]\" stuck at GND" {  } { { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "62 " "Info: Implemented 62 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "36 " "Info: Implemented 36 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 20 16:01:42 2006 " "Info: Processing ended: Thu Apr 20 16:01:42 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}