dial2.tan.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:cnt_scan_rtl_0\|dffs\[0\] register lpm_counter:cnt_scan_rtl_0\|dffs\[15\] 76.92 MHz 13.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.92 MHz between source register \"lpm_counter:cnt_scan_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:cnt_scan_rtl_0\|dffs\[15\]\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[0\] 1 REG LC1 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 16; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[0\]'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "" { lpm_counter:cnt_scan_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[15\] 2 REG LC102 41 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC102; Fanout = 41; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[15\]'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "8.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[0] lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "8.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[0] lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[0] lpm_counter:cnt_scan_rtl_0|dffs[15] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "" { clk } "NODE_NAME" } "" } } { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[15\] 2 REG LC102 41 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC102; Fanout = 41; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[15\]'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "0.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "" { clk } "NODE_NAME" } "" } } { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[0\] 2 REG LC1 16 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 16; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[0\]'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "0.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "8.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[0] lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[0] lpm_counter:cnt_scan_rtl_0|dffs[15] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[7\] lpm_counter:cnt_scan_rtl_0\|dffs\[13\] 18.000 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[7\]\" through register \"lpm_counter:cnt_scan_rtl_0\|dffs\[13\]\" is 18.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "" { clk } "NODE_NAME" } "" } } { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[13\] 2 REG LC98 43 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC98; Fanout = 43; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[13\]'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "0.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[13] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.000 ns + Longest register pin " "Info: + Longest register to pin delay is 14.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt_scan_rtl_0\|dffs\[13\] 1 REG LC98 43 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC98; Fanout = 43; REG Node = 'lpm_counter:cnt_scan_rtl_0\|dffs\[13\]'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "" { lpm_counter:cnt_scan_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns data4\[0\]~141 2 COMB LC87 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC87; Fanout = 1; COMB Node = 'data4\[0\]~141'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "8.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[13] data4[0]~141 } "NODE_NAME" } "" } } { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 10.000 ns data4\[0\]~128 3 COMB LC88 1 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 10.000 ns; Loc. = LC88; Fanout = 1; COMB Node = 'data4\[0\]~128'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "2.000 ns" { data4[0]~141 data4[0]~128 } "NODE_NAME" } "" } } { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 14.000 ns dataout\[7\] 4 PIN PIN_57 0 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 14.000 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'dataout\[7\]'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "4.000 ns" { data4[0]~128 dataout[7] } "NODE_NAME" } "" } } { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.000 ns 85.71 % " "Info: Total cell delay = 12.000 ns ( 85.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 14.29 % " "Info: Total interconnect delay = 2.000 ns ( 14.29 % )" {  } {  } 0}  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "14.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[13] data4[0]~141 data4[0]~128 dataout[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "14.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[13] data4[0]~141 data4[0]~128 dataout[7] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 2.000ns 4.000ns } } }  } 0}  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "3.000 ns" { clk lpm_counter:cnt_scan_rtl_0|dffs[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:cnt_scan_rtl_0|dffs[13] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "14.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[13] data4[0]~141 data4[0]~128 dataout[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "14.000 ns" { lpm_counter:cnt_scan_rtl_0|dffs[13] data4[0]~141 data4[0]~128 dataout[7] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 2.000ns 4.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "datain\[7\] dataout\[7\] 16.000 ns Longest " "Info: Longest tpd from source pin \"datain\[7\]\" to destination pin \"dataout\[7\]\" is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns datain\[7\] 1 PIN PIN_15 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 4; PIN Node = 'datain\[7\]'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "" { datain[7] } "NODE_NAME" } "" } } { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns data4\[0\]~141 2 COMB LC87 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC87; Fanout = 1; COMB Node = 'data4\[0\]~141'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "8.000 ns" { datain[7] data4[0]~141 } "NODE_NAME" } "" } } { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 12.000 ns data4\[0\]~128 3 COMB LC88 1 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 12.000 ns; Loc. = LC88; Fanout = 1; COMB Node = 'data4\[0\]~128'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "2.000 ns" { data4[0]~141 data4[0]~128 } "NODE_NAME" } "" } } { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 16.000 ns dataout\[7\] 4 PIN PIN_57 0 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 16.000 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'dataout\[7\]'" {  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "4.000 ns" { data4[0]~128 dataout[7] } "NODE_NAME" } "" } } { "dial2.vhd" "" { Text "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/dial2.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 87.50 % " "Info: Total cell delay = 14.000 ns ( 87.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 12.50 % " "Info: Total interconnect delay = 2.000 ns ( 12.50 % )" {  } {  } 0}  } { { "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" "" { Report "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2_cmp.qrpt" Compiler "dial2" "UNKNOWN" "V1" "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/db/dial2.quartus_db" { Floorplan "E:/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/接口实验/拨码开关/dial2/" "" "16.000 ns" { datain[7] data4[0]~141 data4[0]~128 dataout[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.000 ns" { datain[7] datain[7]~out data4[0]~141 data4[0]~128 dataout[7] } { 0.000ns 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 2.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 20 16:01:48 2006 " "Info: Processing ended: Thu Apr 20 16:01:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}