serial.map.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 21 17:11:07 2005 " "Info: Processing started: Mon Nov 21 17:11:07 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off serial -c serial " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serial -c serial" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serial.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file serial.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 serial-arch " "Info: Found design unit 1: serial-arch" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 31 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 serial " "Info: Found entity 1: serial" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 19 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "serial " "Info: Elaborating entity \"serial\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "36 " "Info: Ignored 36 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "36 " "Info: Ignored 36 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 48 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "txd_buf\[7\] data_in GND " "Warning: Reduced register \"txd_buf\[7\]\" with stuck data_in port to stuck value GND" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 50 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning: Pin \"en\[0\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] GND " "Warning: Pin \"en\[1\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] GND " "Warning: Pin \"en\[2\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] GND " "Warning: Pin \"en\[3\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] GND " "Warning: Pin \"en\[4\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] GND " "Warning: Pin \"en\[5\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] GND " "Warning: Pin \"en\[6\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] GND " "Warning: Pin \"en\[7\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg_data\[0\] VCC " "Warning: Pin \"seg_data\[0\]\" stuck at VCC" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 26 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lowbit GND " "Warning: Pin \"lowbit\" stuck at GND" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 28 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "156 " "Info: Implemented 156 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "112 " "Info: Implemented 112 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "22 " "Info: Implemented 22 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 21 17:11:45 2005 " "Info: Processing ended: Mon Nov 21 17:11:45 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Info: Elapsed time: 00:00:40" {  } {  } 0}  } {  } 0}