serial.tan.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Info" "ITDB_TH_RESULT" "rxd_reg1 rxd clk 6.000 ns register " "Info: th for register \"rxd_reg1\" (data pin = \"rxd\", clock pin = \"clk\") is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 39 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 39; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/" "" "" { clk } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns clkbaud8x 2 REG LC17 40 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC17; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/" "" "1.000 ns" { clk clkbaud8x } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns rxd_reg1 3 REG LC96 2 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC96; Fanout = 2; REG Node = 'rxd_reg1'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/" "" "8.000 ns" { clkbaud8x rxd_reg1 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/" "" "12.000 ns" { clk clkbaud8x rxd_reg1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out clkbaud8x rxd_reg1 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns rxd 1 PIN PIN_25 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_25; Fanout = 1; PIN Node = 'rxd'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/" "" "" { rxd } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns rxd_reg1 2 REG LC96 2 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC96; Fanout = 2; REG Node = 'rxd_reg1'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/" "" "8.000 ns" { rxd rxd_reg1 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/serial.vhd" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/" "" "10.000 ns" { rxd rxd_reg1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { rxd rxd~out rxd_reg1 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/" "" "12.000 ns" { clk clkbaud8x rxd_reg1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out clkbaud8x rxd_reg1 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/db/serial.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/串口/" "" "10.000 ns" { rxd rxd_reg1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { rxd rxd~out rxd_reg1 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 21 17:12:07 2005 " "Info: Processing ended: Mon Nov 21 17:12:07 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}