key0.fit.summary

CPLD开发板VHDL源程序并附上开发板的原理图

Flow Status : Successful - Wed Nov 23 15:43:14 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : key0
Top-level Entity Name : key0
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 47 / 128 ( 36 % )
Total pins : 30 / 68 ( 44 % )