key0.tan.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[5\] key_code\[1\] 17.000 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[5\]\" through register \"key_code\[1\]\" is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "" { clk } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns key_code\[1\] 2 REG LC53 26 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC53; Fanout = 26; REG Node = 'key_code\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "0.000 ns" { clk key_code[1] } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk key_code[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out key_code[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_code\[1\] 1 REG LC53 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC53; Fanout = 26; REG Node = 'key_code\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "" { key_code[1] } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns Mux~1758 2 COMB LC97 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC97; Fanout = 1; COMB Node = 'Mux~1758'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "9.000 ns" { key_code[1] Mux~1758 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns dataout\[5\] 3 PIN PIN_63 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'dataout\[5\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "4.000 ns" { Mux~1758 dataout[5] } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "13.000 ns" { key_code[1] Mux~1758 dataout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { key_code[1] Mux~1758 dataout[5] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk key_code[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out key_code[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "13.000 ns" { key_code[1] Mux~1758 dataout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { key_code[1] Mux~1758 dataout[5] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "key_code\[1\] column\[2\] clk -3.000 ns register " "Info: th for register \"key_code\[1\]\" (data pin = \"column\[2\]\", clock pin = \"clk\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "" { clk } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns key_code\[1\] 2 REG LC53 26 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC53; Fanout = 26; REG Node = 'key_code\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "0.000 ns" { clk key_code[1] } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk key_code[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out key_code[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns column\[2\] 1 PIN PIN_37 24 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_37; Fanout = 24; PIN Node = 'column\[2\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "" { column[2] } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns key_code\[1\] 2 REG LC53 26 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC53; Fanout = 26; REG Node = 'key_code\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "8.000 ns" { column[2] key_code[1] } "NODE_NAME" } "" } } { "key0.vhd" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/key0.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "10.000 ns" { column[2] key_code[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { column[2] column[2]~out key_code[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "3.000 ns" { clk key_code[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out key_code[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0_cmp.qrpt" Compiler "key0" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/db/key0.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/VHDL/接口实验/矩阵键盘/key0/" "" "10.000 ns" { column[2] key_code[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { column[2] column[2]~out key_code[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 23 15:43:18 2005 " "Info: Processing ended: Wed Nov 23 15:43:18 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}