key0.tan.rpt

CPLD开发板VHDL源程序并附上开发板的原理图

; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                               ; To                                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[20] ; key_code[3]                        ; clk        ; clk      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; key_code[3]                        ; key_code[3]                        ; clk        ; clk      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[19] ; key_code[2]                        ; clk        ; clk      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 71.43 MHz ( period = 14.000 ns )                    ; key_code[2]                        ; key_code[2]                        ; clk        ; clk      ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[15] ; lpm_counter:div_cnt_rtl_0|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[16] ; lpm_counter:div_cnt_rtl_0|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[17] ; lpm_counter:div_cnt_rtl_0|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[18] ; lpm_counter:div_cnt_rtl_0|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[19] ; lpm_counter:div_cnt_rtl_0|dffs[19] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[0]  ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[1]  ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[2]  ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[3]  ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[4]  ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[5]  ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[6]  ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[7]  ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[8]  ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[9]  ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[10] ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[11] ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[12] ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[13] ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[14] ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[15] ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[16] ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[17] ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[18] ; lpm_counter:div_cnt_rtl_0|dffs[18] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; lpm_counter:div_cnt_rtl_0|dffs[0]  ; lpm_counter:div_cnt_rtl_0|dffs[17] ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;