add.tan.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 15 09:11:18 2006 " "Info: Processing started: Sat Apr 15 09:11:18 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off add -c add " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off add -c add" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[2\] c\[4\] 25.000 ns Longest " "Info: Longest tpd from source pin \"a\[2\]\" to destination pin \"c\[4\]\" is 25.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a\[2\] 1 PIN PIN_21 66 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_21; Fanout = 66; PIN Node = 'a\[2\]'" {  } { { "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" "" { Report "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add.quartus_db" { Floorplan "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/" "" "" { a[2] } "NODE_NAME" } "" } } { "add.vhd" "" { Text "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/add.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns Mux~2866 2 COMB LC1 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC1; Fanout = 1; COMB Node = 'Mux~2866'" {  } { { "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" "" { Report "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add.quartus_db" { Floorplan "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/" "" "8.000 ns" { a[2] Mux~2866 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 12.000 ns Mux~2824 3 COMB LC2 1 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 12.000 ns; Loc. = LC2; Fanout = 1; COMB Node = 'Mux~2824'" {  } { { "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" "" { Report "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add.quartus_db" { Floorplan "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/" "" "2.000 ns" { Mux~2866 Mux~2824 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 21.000 ns Mux~2832 4 COMB LC93 1 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 21.000 ns; Loc. = LC93; Fanout = 1; COMB Node = 'Mux~2832'" {  } { { "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" "" { Report "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add.quartus_db" { Floorplan "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/" "" "9.000 ns" { Mux~2824 Mux~2832 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 25.000 ns c\[4\] 5 PIN PIN_60 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 25.000 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'c\[4\]'" {  } { { "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" "" { Report "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add.quartus_db" { Floorplan "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/" "" "4.000 ns" { Mux~2832 c[4] } "NODE_NAME" } "" } } { "add.vhd" "" { Text "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/add.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 84.00 % " "Info: Total cell delay = 21.000 ns ( 84.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 16.00 % " "Info: Total interconnect delay = 4.000 ns ( 16.00 % )" {  } {  } 0}  } { { "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" "" { Report "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/db/add.quartus_db" { Floorplan "E:/information/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/基础实验/加法器/" "" "25.000 ns" { a[2] Mux~2866 Mux~2824 Mux~2832 c[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { a[2] a[2]~out Mux~2866 Mux~2824 Mux~2832 c[4] } { 0.000ns 0.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 15 09:11:19 2006 " "Info: Processing ended: Sat Apr 15 09:11:19 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}