mux.tan.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 23 21:43:51 2005 " "Info: Processing started: Fri Sep 23 21:43:51 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[1\] d\[2\] 23.000 ns Longest " "Info: Longest tpd from source pin \"b\[1\]\" to destination pin \"d\[2\]\" is 23.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns b\[1\] 1 PIN PIN_22 13 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_22; Fanout = 13; PIN Node = 'b\[1\]'" {  } { { "E:/work1/mux/db/mux_cmp.qrpt" "" { Report "E:/work1/mux/db/mux_cmp.qrpt" Compiler "mux" "UNKNOWN" "V1" "E:/work1/mux/db/mux.quartus_db" { Floorplan "E:/work1/mux/" "" "" { b[1] } "NODE_NAME" } "" } } { "mux.vhd" "" { Text "E:/work1/mux/mux.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 12.000 ns Mux~546 2 COMB SEXP94 1 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP94; Fanout = 1; COMB Node = 'Mux~546'" {  } { { "E:/work1/mux/db/mux_cmp.qrpt" "" { Report "E:/work1/mux/db/mux_cmp.qrpt" Compiler "mux" "UNKNOWN" "V1" "E:/work1/mux/db/mux.quartus_db" { Floorplan "E:/work1/mux/" "" "10.000 ns" { b[1] Mux~546 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 19.000 ns Mux~552 3 COMB LC86 1 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC86; Fanout = 1; COMB Node = 'Mux~552'" {  } { { "E:/work1/mux/db/mux_cmp.qrpt" "" { Report "E:/work1/mux/db/mux_cmp.qrpt" Compiler "mux" "UNKNOWN" "V1" "E:/work1/mux/db/mux.quartus_db" { Floorplan "E:/work1/mux/" "" "7.000 ns" { Mux~546 Mux~552 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 23.000 ns d\[2\] 4 PIN PIN_56 0 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 23.000 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'd\[2\]'" {  } { { "E:/work1/mux/db/mux_cmp.qrpt" "" { Report "E:/work1/mux/db/mux_cmp.qrpt" Compiler "mux" "UNKNOWN" "V1" "E:/work1/mux/db/mux.quartus_db" { Floorplan "E:/work1/mux/" "" "4.000 ns" { Mux~552 d[2] } "NODE_NAME" } "" } } { "mux.vhd" "" { Text "E:/work1/mux/mux.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 91.30 % " "Info: Total cell delay = 21.000 ns ( 91.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.70 % " "Info: Total interconnect delay = 2.000 ns ( 8.70 % )" {  } {  } 0}  } { { "E:/work1/mux/db/mux_cmp.qrpt" "" { Report "E:/work1/mux/db/mux_cmp.qrpt" Compiler "mux" "UNKNOWN" "V1" "E:/work1/mux/db/mux.quartus_db" { Floorplan "E:/work1/mux/" "" "23.000 ns" { b[1] Mux~546 Mux~552 d[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { b[1] b[1]~out Mux~546 Mux~552 d[2] } { 0.000ns 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 2.000ns 8.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 23 21:43:52 2005 " "Info: Processing ended: Fri Sep 23 21:43:52 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}