clock.map.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 23 16:37:19 2006 " "Info: Processing started: Mon Oct 23 16:37:19 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.bdf" "" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decode47.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decode47.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decode47-behave " "Info: Found design unit 1: decode47-behave" {  } { { "decode47.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/decode47.vhd" 22 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 decode47 " "Info: Found entity 1: decode47" {  } { { "decode47.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/decode47.vhd" 15 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sel.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sel.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sel-behave " "Info: Found design unit 1: sel-behave" {  } { { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 35 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sel " "Info: Found entity 1: sel" {  } { { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen60.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fen60.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen60-behave " "Info: Found design unit 1: fen60-behave" {  } { { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 26 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fen60 " "Info: Found entity 1: fen60" {  } { { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen24.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fen24.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen24-behave " "Info: Found design unit 1: fen24-behave" {  } { { "fen24.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen24.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fen24 " "Info: Found entity 1: fen24" {  } { { "fen24.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen24.vhd" 17 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fen1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen1-behave " "Info: Found design unit 1: fen1-behave" {  } { { "fen1.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen1.vhd" 23 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fen1 " "Info: Found entity 1: fen1" {  } { { "fen1.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen1.vhd" 15 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen100.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fen100.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen100-behave " "Info: Found design unit 1: fen100-behave" {  } { { "fen100.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen100.vhd" 24 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fen100 " "Info: Found entity 1: fen100" {  } { { "fen100.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen100.vhd" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode47 decode47:inst6 " "Info: Elaborating entity \"decode47\" for hierarchy \"decode47:inst6\"" {  } { { "clock.bdf" "inst6" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 0 672 816 96 "inst6" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sel sel:inst5 " "Info: Elaborating entity \"sel\" for hierarchy \"sel:inst5\"" {  } { { "clock.bdf" "inst5" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { -16 424 568 176 "inst5" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fen100 fen100:inst2 " "Info: Elaborating entity \"fen100\" for hierarchy \"fen100:inst2\"" {  } { { "clock.bdf" "inst2" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { -80 48 144 16 "inst2" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fen60 fen60:inst3 " "Info: Elaborating entity \"fen60\" for hierarchy \"fen60:inst3\"" {  } { { "clock.bdf" "inst3" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 16 192 312 112 "inst3" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tem1 fen60.vhd(49) " "Warning: VHDL Process Statement warning at fen60.vhd(49): signal \"tem1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tem2 fen60.vhd(50) " "Warning: VHDL Process Statement warning at fen60.vhd(50): signal \"tem2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fen60.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen60.vhd" 50 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fen1 fen1:inst " "Info: Elaborating entity \"fen1\" for hierarchy \"fen1:inst\"" {  } { { "clock.bdf" "inst" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 16 48 144 112 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fen24 fen24:inst4 " "Info: Elaborating entity \"fen24\" for hierarchy \"fen24:inst4\"" {  } { { "clock.bdf" "inst4" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 272 192 312 368 "inst4" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tem1 fen24.vhd(55) " "Warning: VHDL Process Statement warning at fen24.vhd(55): signal \"tem1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fen24.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen24.vhd" 55 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tem2 fen24.vhd(56) " "Warning: VHDL Process Statement warning at fen24.vhd(56): signal \"tem2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fen24.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen24.vhd" 56 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/program files/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "41 " "Info: Ignored 41 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "41 " "Info: Ignored 41 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "fen1:inst\|cnt\[0\] fen100:inst2\|cnt\[0\] " "Info: Duplicate register \"fen1:inst\|cnt\[0\]\" merged to single register \"fen100:inst2\|cnt\[0\]\"" {  } { { "fen1.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen1.vhd" 27 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 31 -1 0 } } { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 31 -1 0 } } { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 31 -1 0 } } { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 31 -1 0 } } { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 31 -1 0 } } { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 31 -1 0 } } { "sel.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/sel.vhd" 31 -1 0 } } { "fen24.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen24.vhd" 29 -1 0 } } { "fen24.vhd" "" { Text "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/fen24.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[0\] VCC " "Warning: Pin \"seg\[0\]\" stuck at VCC" {  } { { "clock.bdf" "" { Schematic "E:/work_room/EDA/Mars-7128-S Altera CPLD开发板/示例程序/VHDL/综合实验/数字时钟/clock.bdf" { { 24 816 992 40 "seg\[7..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "132 " "Info: Implemented 132 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "114 " "Info: Implemented 114 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 23 16:37:28 2006 " "Info: Processing ended: Mon Oct 23 16:37:28 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}